1 title "PIC16F870 Unilink(R) Interface by Werner Johansson, wj@yodel.net"
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2 subtitl "Definitions"
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3 list c=150,P=16F870,R=DEC,F=inhx8m
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4 include "p16f870.inc" ; Standard equates & Macros
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5 ERRORLEVEL 1,-302 ; Get rid of those annoying 302 msgs!
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7 ;******************************************************************************
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9 ; This program is free software; you can redistribute it and/or modify
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10 ; it under the terms of the GNU General Public License as published by
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11 ; the Free Software Foundation; either version 2 of the License, or
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12 ; (at your option) any later version.
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14 ; This program is distributed in the hope that it will be useful,
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15 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 ; GNU General Public License for more details.
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19 ; You should have received a copy of the GNU General Public License
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20 ; along with this program; if not, write to the Free Software
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21 ; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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23 ; Author: Werner Johansson (wj@yodel.net), with some code and ideas from
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24 ; Simon Woods' GNUnilink, radix conversion utilities from piclist.com
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25 ; and of course the reverse-engineered Unilink(R) command list
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27 ;******************************************************************************
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29 ;----------------------------------------------------------------
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30 ; The Configuration Word
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31 __CONFIG _HS_OSC&_WDT_OFF&_PWRTE_ON&_BODEN_ON&_LVP_OFF&_CPD_OFF&_WRT_ENABLE_ON&_DEBUG_OFF&_CP_OFF
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33 ;----------------------------------------------------------------
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35 ;----------------------------------------------------------------
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36 ; Investigate whether I actually have to save PCLATH in ISH, maybe save FSR? - Not saving any of them for now
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37 ; Check Overrun errors from the UART
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38 ; Implement lots of other Unilink commands (Text display, time display etc.)
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39 ; Implement the Watchdog Timer (might be useful even though I haven't seen it hang yet..)
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40 ; Make the bit shift routine at the beginning of the ISR timeout if the clock suddenly stops (in the middle of a byte)
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41 ; (will keep it from hanging until the next bit gets clocked out, just ignore the faulty bits and carry on)
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42 ; Implement command b0 0x (change CD to x (1-a))
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43 ; Implement command 08 10 (Tel Mute on) and 08 18 (Tel Mute off)?
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45 ;----------------------------------------------------------------
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47 ;----------------------------------------------------------------
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50 ; 0.8 Some text commands implemented, only static text for now though
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51 ; 0.7 Debug Serial TX in ISR now, checksum check for incoming packets in place, A/D works, solved the master reset prob
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52 ; (by calling the INT handler from TMR2 ISR code (too much interrupt latency when transmitting)
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53 ; 0.6 Some more LCD info and clean-up of the Unilink recovery code, some problems with master resetting :(
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54 ; 0.5 Issues slave breaks seemingly without hickups (!)
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55 ; 0.4 Some fixups in the bootstrap code (I actually had to put the PIC in my PICSTART Plus programmer again :))
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56 ; 0.3 Implementing more Unilink commands and RingIndicator control (to wake the computer from sleep)
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57 ; 0.2 First attempt at responding to the Anyone command
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58 ; 0.1 Receives Unilink data OK, relays it to serial
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59 ; 0.0 Very first "F**king No Work!" version
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61 ;----------------------------------------------------------------
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63 ;----------------------------------------------------------------
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64 ; Unilink BUSON IN (blue) connected to RC2/CCP1
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65 ; Unilink DATA (green) connected to RC3
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66 ; Unilink BUSON OUT (blue) connected to RC4 (this is for daisy-chaining)
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67 ; Unilink CLK (yellow) connected to RB0/INT (Interrupt pin)
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68 ; Unilink RST (lilac) connected to RA4
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69 ; LCD RS connected to pin RB1 (The LCD is a standard 16x1 char HD44780 compatible unit)
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70 ; LCD RW connected to pin RB2
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71 ; LCD E connected to pin RB3
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72 ; LCD DB4-DB7 connected to RB4-RB7
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73 ; RS-232 TX from computer connected to RC7/RX
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74 ; RS-232 RX to computer connected to RC6/TX
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75 ; RS-232 RI to computer connected to RC5
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76 ; B+ connected via trimmer and resistors to AN0 (divider approx 20k5/5k to give 20.48V maximum scale)
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78 ; This leaves RC0, RC1 and four analog inputs (AN1-AN4) free for now...
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80 #define BUSON_IN_BIT PORTC,2
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81 #define DATA_BIT PORTC,3
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82 #define BUSON_OUT_BIT PORTC,4
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83 #define CLK_BIT PORTB,0
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84 #define RST_BIT PORTA,4
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86 #define LCD_RS_BIT PORTB,1
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87 #define LCD_RW_BIT PORTB,2
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88 #define LCD_E_BIT PORTB,3
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89 #define LCD_DB4_BIT PORTB,4
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90 #define LCD_DB5_BIT PORTB,5
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91 #define LCD_DB6_BIT PORTB,6
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92 #define LCD_DB7_BIT PORTB,7
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94 #define RS232_RI_BIT PORTC,5
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96 ;----------------------------------------------------------------
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97 ; FILE REGISTER USAGE
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98 ;----------------------------------------------------------------
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101 UnilinkRAD equ 50h ; Beginning of Unilink packet - the Receiving Address
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102 UnilinkTAD equ 51h ; Transmitter address
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103 UnilinkCMD1 equ 52h ; CMD1 byte
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104 UnilinkCMD2 equ 53h ; CMD2 byte
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105 UnilinkParity1 equ 54h ; First or only parity byte for short packets (6 bytes)
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106 UnilinkData1 equ 55h ; Extra data for medium/large packets, or zero for short packets
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107 UnilinkData2 equ 56h ;
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108 UnilinkData3 equ 57h ;
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109 UnilinkData4 equ 58h ;
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110 UnilinkData5 equ 59h ; Data5 if this is a large packet
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111 UnilinkParity2M equ 59h ; Parity2 shares the same byte if it's a medium sized packet
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112 UnilinkData6 equ 5ah ; Extra data for large packets, or zero for medium packets
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113 UnilinkData7 equ 5bh ;
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114 UnilinkData8 equ 5ch ;
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115 UnilinkData9 equ 5dh ;
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116 UnilinkParity2 equ 5eh ; Parity byte for large packets
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117 UnilinkZero equ 5fh ; Should always be zero (possibly used to signal corrupt packets from slave to master?)
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119 UnilinkTimeout equ 60h ; Counts up every 0.5ms to "age out" faulty bytes clocked in
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120 UnilinkSelected equ 61h ; High bit is set when selected
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121 UnilinkBit equ 62h ; This is my "bitmask" to be used for requests
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122 UnilinkID equ 63h ; This is my Bus ID
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123 UnilinkCmdLen equ 64h ; This gets updated with the actual packet length after CMD1 has been received
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124 UnilinkTXRX equ 65h ; This is a pointer to the Unilink packet above, used with indirect addressing
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125 SlaveBreakState equ 66h ; Hold state and time-out information about slave break, indicates when it can happen
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126 DisplayStatus equ 67h ; What information will be put on the display next, bit 7 cleared if nothing
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127 Icount equ 68h ; Offset of string to print
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128 TxTemp equ 69h ; blahblah
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129 TxTemp2 equ 6ah ; Blahblah2
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137 DataCount equ 71h ; Temp storage for the bit counter used during bit shifts (Unilink TX/RX)
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138 UnilinkCurID equ 72h ; This is a kludge
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139 DisplayCounter equ 73h
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140 UnilinkAttenuation equ 74h ; The amount of attenuation the volume control is currently set to
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148 UnilinkReInits equ 7ch
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149 IRQPCLATH equ 7dh ; ISH storage
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150 IRQSTATUS equ 7eh ; Needs to be located in a shared area accessible from all register banks
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153 RecvBuf equ 0a0h ; Buffer for received data from PC (31 bytes)
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154 RecvBufLen equ 0bfh ; How many bytes have been received?
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158 ;----------------------------------------------------------------
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159 ; Power up/Reset starting point
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161 org 0 ; Start at the beginning of memory (the reset vector)
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162 call Bootstrap ; Call Flash Load routine
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163 call LCDInit ; Initialize LCD I/F
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164 call IRQInit ; Set up and start the IRQ handler
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165 goto Main ; Run the main program loop (skip the IRQ handler)
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167 subtitl "IRQ Handler"
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168 ;----------------------------------------------------------------
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169 ; Interrupt handler always starts at addr 4
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170 ; In order to reduce the INT latency the actual code is put here directly instead of using a goto instruction.
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171 ; Also because of the real-time requirements for clocking data onto the Unilink bus the first check in the ISR
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172 ; is to see whether the Unilink clock rise was the reason for the interrupt. This results in a "clock rise to
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173 ; bit ready" time of less than 30 instruction cycles, should be plenty of spare time waiting for clock to go low
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174 ; again after that. Other interrupts might introduce latencies, but let's see how this works..
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176 org 4 ; ISR vector is at address 4
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177 movwf IRQW ; Save W
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178 swapf STATUS,w ; Get the status register into w
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179 clrf STATUS ; Zero out the status reg, gives Reg Bank0
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180 movwf IRQSTATUS ; Store the STATUS reg
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181 ; Not using PCLATH for anything in the ISR right now
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182 ; movf PCLATH,w ; Get the PCLATH reg
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183 ; movwf IRQPCLATH ; And store it
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184 ; clrf PCLATH ; Go to low memory
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185 ; Maybe save FSR here as well (if there's a need for it in the non-ISR code)
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187 call IRQCheckINT ; Implemented as a subroutine as there's a need to call it repeatedly from the other ISRs
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189 btfss PIR1,TMR2IF ; Check if it's the TMR2 interrupt (0.5ms timing)
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190 goto IRQNotTMR2 ; No it's not, check the other sources
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192 incf Counter,f ; Increment the general purpose counter (increments every 0.5ms)
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194 ; Slave break opportunity detection here - the logic works as follows:
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195 ; Look for a data low period of at least 5 ms (10 loops)
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196 ; Look for a data high period of at least 2 ms (4 loops)
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197 ; If the Slave Break request bit has been set, issue a slave break by holding the data line low for 4ms (8 loops)
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198 ; If a bit would be received (CLK activates) the packet handler automatically clears out the SlaveBreakState, which means start all over
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200 call IRQCheckINT ; Check the Unilink INT as well
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202 btfsc SlaveBreakState,5 ; Check if already pulling the data line low
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203 goto IRQTMR2SlaveBreak
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205 btfsc SlaveBreakState,7 ; Looking for low or high data
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206 goto IRQTMR2HighData
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207 btfss DATA_BIT ; Looking for a low data line, if it's low, increment state, if it's high, reset state
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208 goto IRQTMR2LowDataOK
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209 clrf SlaveBreakState ; Got a high data line while waiting for a low one, reset state
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211 call IRQCheckINT ; Check the Unilink INT as well
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213 goto IRQAfterTMR2 ; Leave ISR
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216 call IRQCheckINT ; Check the Unilink INT as well
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218 btfsc DATA_BIT ; Looking for a high data line, if it's high - increment state, otherwise wait
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219 goto IRQTMR2HighDataOK
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221 btfsc SlaveBreakState,6 ; Test the "first time around" bit
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222 clrw ; Not the beginning of the state, have to restart the entire thing now, not just this state
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223 andwf SlaveBreakState,f ; Mask out the 1 upper control bits and restart this state
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228 call IRQCheckINT ; Check the Unilink INT as well
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230 bsf SlaveBreakState,6 ; Set the "first time around" bit
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232 movf SlaveBreakState,w
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235 btfss SlaveBreakState,7 ; Checking whether it's low or high
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236 goto IRQTMR2FoundLow
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238 xorlw 4 ; It's high now, and if 4 periods have passed we can activate slave break
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242 ; Issue slave break here
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244 clrf SlaveBreakState
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248 btfss DisplayStatus,7 ; Only do this if high bit is set
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252 movwf SlaveBreakState
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264 call IRQCheckINT ; Check the Unilink INT as well
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266 movlw 80h ; Prepare for state 2, looking for data line high
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267 movwf SlaveBreakState
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271 call IRQCheckINT ; Check the Unilink INT as well
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273 movf SlaveBreakState,w
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281 clrf SlaveBreakState
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284 btfss SlaveBreakState,4 ; Only increment to 0x10
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285 incf SlaveBreakState,f
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286 bcf PIR1,TMR2IF ; Clear the IRQ source bit to re-enable TMR2 interrupts again
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290 ; Finally restore CPU state and return from the ISR
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292 ; If I have to save the FSR in the beginning I also need to restore it here...
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295 ; movwf PCLATH ; Restore PCLATH
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297 movwf STATUS ; Restore STATUS
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299 swapf IRQW,w ; Restore W
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300 retfie ; Interrupt return
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302 ;----------------------------------------------------------------
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303 ; IRQCheckINT - This part is the actual Unilink tranceiver, have to call it often as there are only ~20 spare cycles
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304 ; (which is only a problem if we're going to transmit, but the check can be done anyway, it's cheap if no bit is there)
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307 btfss INTCON,INTF ; Check if it's the INT edge interrupt (Unilink CLK)
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308 return ; No it's not, return again after only four cycles
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310 ; If there's activity on the clock line (the clock goes high) the CPU will stay in here until eight bits have been clocked in
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311 ; - this reduces context switching (and it's just a few hundred cpu cycles after all (20us*8 bits=160us=800 instruction
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312 ; cycles (5 MIPS @ 20MHz), not even a problem for serial input if it's not receiving more than 6250 bytes per second, and the
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313 ; 2-byte FIFO somehow fills up (this should be impossible even @ 115200 as this blocking INT handler only runs a maximum of
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314 ; 1000 times per second, halting INT's for 1/6250 of a second - this gives the CPU ample of time to deal with all bytes from
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315 ; the USART. I should check the OERR (Serial Overrun) bit to catch this though.. Note that this piece of code does both TX
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316 ; and RX at the same time (in order to receive packets one has to make sure that the packet buffer is zeroed out before entering
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317 ; here, otherwise collisions will occur..
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318 ; According to my logic analyzer this implementation is pretty decent when it comes to timing, even though it's an
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319 ; interrupt driven "USART" implemented in software - by trigging the interrupt on the rising edge there's some extra margin here
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320 ; (the clock goes high 10us before the master clocks the bit in (on the falling edge), that should be plenty of time..)
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322 movlw 8 ; Loop through the 8 bits
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324 movf UnilinkTXRX,w ; Get the pointer
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325 movwf FSR ; Store it to make use of indirect addressing
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328 btfss INDF,7 ; Test high bit of data (that's the first bit to be clocked out)
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329 goto IRQINTTristate ; Bit is low, we should tristate bit
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330 bcf PORTC,3 ; Otherwise set DATA bit low
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331 bsf STATUS,RP0 ; Select high regs
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332 bcf TRISC,3 ; And pull low (now it's an output)
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333 bcf STATUS,RP0 ; Back to regbank 0
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334 goto IRQINTCLKWaitLow ; Wait for master to actually clock this bit in
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337 bsf STATUS,RP0 ; Select high regs
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338 bsf TRISC,3 ; Force the bit to be tristated
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339 bcf STATUS,RP0 ; Back to regbank 0
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342 btfss PORTC,2 ; Check for BUSON
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344 btfsc PORTB,0 ; Wait for clock to go low
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345 goto IRQINTCLKWaitLow
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348 btfss PORTC,3 ; Test DATA
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349 setc ; Set carry if data is LOW (data is inverted!)
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350 rlf INDF,f ; Shift it into the "accumulator"
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352 decfsz DataCount,f ; Loop once more perhaps?
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353 goto IRQINTCLKWaitHigh ; Yes, again!
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354 goto IRQINTRecvDone ; No it's done, don't check for clock to go high again
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357 btfss PORTC,2 ; Check for BUSON
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359 btfss PORTB,0 ; Wait for clock to go high
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360 goto IRQINTCLKWaitHigh
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361 goto IRQINTBitSet ; Loop again
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363 ; Successfully received a byte here, run it through a state machine to figure out what to do
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364 ; (several possibilites exists here):
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365 ;;;;;; If more than 1.1ms has passed since last receive, reset receive counter to zero
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366 ; If receive counter is zero and the received byte is a zero byte, discard it
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367 ; Otherwise store the byte in our receive buffer and increment receive counter
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368 ; If the receive counter is 3 check the two upper bits of recv'd byte (CMD1) - this tells us the length of the packet
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369 ; 00 = short 6 byte packet
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370 ; 10 = medium 11 byte packet
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371 ; 11 = long 16 byte packet
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372 ; Update the receive length byte accordingly
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373 ; Check whether receive length and receive count are equal, that means that we're finished and we can carry on parsing
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374 ; the packet and take appropriate action.
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377 clrf SlaveBreakState ; First of all, clear the break state - this got in the way, restart detection..
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380 call BootTXB ; Send the byte to the serial port
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382 movf UnilinkTXRX,w ; Find out which byte # that was received
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384 bnz IRQINTRecvNotFirst ; Not the first byte
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385 movf UnilinkRAD,w ; Get the first byte received
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386 bz IRQINTRecvNullByte ; Null byte received, ignore this, don't increment counter
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388 incf UnilinkTXRX,f ; Increment address
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390 movf UnilinkTXRX,w ; Get the byte position again
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391 andlw 0fh ; Only lower 4 bits of interest
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392 xorlw 03h ; Well, is it the third byte? (CMD1, telling us the length of the packet)
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393 bnz IRQINTRecvNotCMD1 ; No, skip the length code for now
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394 movlw 6 ; Assume it's a short packet
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395 btfss INDF,7 ; INDF still points to received byte, test high bit for medium/long
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396 goto IRQINTRecvShort ; Nope, it's a short packet
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397 addlw 5 ; OK, it's long or medium at least
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398 btfsc INDF,6 ; Test for long
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399 addlw 5 ; Yep, it's a long packet
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401 movwf UnilinkCmdLen ; Store the length
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404 movf UnilinkTXRX,w ; Get the byte position
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405 xorwf UnilinkCmdLen,w ; XOR with the calculated command length
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406 andlw 0fh ; and mask - this results in a zero result when finished receiving
\r
407 bnz IRQINTRecvIncomplete ; Packet not ready yet
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409 ; Here a packet is actually received, should check the checksum(s) now
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411 movf UnilinkRAD,w ; QnD checksum check
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413 addwf UnilinkCMD1,w
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414 addwf UnilinkCMD2,w
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415 xorwf UnilinkParity1,w ; This should be zero
\r
416 bnz IRQINTParseComplete ; Don't allow packet parsing on corrupt packets
\r
418 btfss UnilinkCMD1,7 ; Test whether there's more parity to check (medium or long packet)
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419 goto IRQINTParser ; No, skip directly to parsing logic
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421 movf UnilinkParity1,w ; QnD checksum check for the remaining part of the packet
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422 addwf UnilinkData1,w
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423 addwf UnilinkData2,w
\r
424 addwf UnilinkData3,w
\r
425 addwf UnilinkData4,w
\r
427 btfss UnilinkCMD1,6 ; Test for a long packet
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428 goto IRQINTBypassLongPacket
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430 xorwf UnilinkParity2M,w ; Fix for the medium packet parity check a few lines down...
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431 addwf UnilinkData5,w
\r
432 addwf UnilinkData6,w
\r
433 addwf UnilinkData7,w
\r
434 addwf UnilinkData8,w
\r
435 addwf UnilinkData9,w
\r
436 xorwf UnilinkParity2,w ; This should be zero when xor:ed with the Parity2M
\r
438 IRQINTBypassLongPacket
\r
439 xorwf UnilinkParity2M,w ; This should be zero for valid medium and long packets
\r
440 bnz IRQINTParseComplete
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444 ; This is inefficient, I know, I'll improve it later... (Not that it matters, there's plenty of time here
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445 ; (there won't be any more communication for at least another 4.8ms))
\r
447 ; Unilink command parser:
\r
449 ; Check for CMD1 = 01h (System bus commands)
\r
452 bnz IRQINTParseNot01
\r
454 ; Check for 01 00 (Bus Re-Initialization)
\r
456 bnz IRQINTParseNot0100
\r
458 call ClearUnilinkStatus ; Clear everything Unilink (ID, BUSON_OUT)
\r
460 incf UnilinkReInits,f ; increment the debug counter
\r
462 goto IRQINTParseComplete ; Don't send any reply to this (clear the packet buffer though)
\r
466 ; Check for 01 02 (Anyone)
\r
469 bnz IRQINTParseNot0102
\r
471 movf UnilinkID,w ; Do I have an ID already?
\r
472 bnz IRQINTParseComplete ; Yep, I don't want another one!
\r
474 call ClearUnilinkBuffer ; Zero it out completely
\r
476 movlw 10h ; Sending to Master
\r
477 addwf UnilinkParity1,f
\r
479 movlw 0d0h ; I'm in the MD changer group
\r
480 addwf UnilinkParity1,f
\r
482 movlw 8ch ; Device discovery command reply
\r
483 addwf UnilinkParity1,f
\r
486 addwf UnilinkParity1,f
\r
489 movf UnilinkParity1,w
\r
490 movwf UnilinkParity2M
\r
492 movlw 24h ; My internal MD sends 25 here first time, and then 24 when appointed!??
\r
493 addwf UnilinkParity2M,f
\r
496 addwf UnilinkParity2M,f
\r
499 addwf UnilinkParity2M,f
\r
501 movlw 0a0h ; 00?? 0a0=10 disc?
\r
502 addwf UnilinkParity2M,f
\r
505 goto IRQINTParseBypassClear ; Don't clear the data, the buffer will be sent as the next packet
\r
509 ; Check for 01 12 (Time poll)
\r
512 bnz IRQINTParseNot0112
\r
515 xorwf UnilinkID,w ; Is it for me?
\r
516 bnz IRQINTParseNot0112 ; Nope
\r
518 call ClearUnilinkBuffer
\r
519 movlw 10h ; Sending to Master
\r
520 addwf UnilinkParity1,f
\r
522 movf UnilinkID,w ; This is my ID
\r
523 addwf UnilinkParity1,f
\r
526 addwf UnilinkParity1,f
\r
529 movlw 80h ; Idle unless selected
\r
530 btfsc UnilinkSelected,7
\r
533 addwf UnilinkParity1,f
\r
535 goto IRQINTParseBypassClear ; Don't clear the data, the buffer will be sent as the next packet
\r
539 ; Check for 01 13 (Request Time poll)
\r
542 bnz IRQINTParseNot0113
\r
545 xorwf UnilinkID,w ; Is it for me?
\r
546 bnz IRQINTParseNot0113 ; Nope
\r
548 btfss DisplayStatus,7 ; If not displaying, skip this
\r
549 goto IRQINTParseComplete
\r
551 call ClearUnilinkBuffer
\r
553 movlw 70h ; Sending to Display Group
\r
554 addwf UnilinkParity1,f
\r
556 movf UnilinkID,w ; This is my ID
\r
557 addwf UnilinkParity1,f
\r
560 movf DisplayStatus,w
\r
561 xorlw 80h ; First slave break?
\r
562 bnz IRQINTParse0113Not80
\r
565 addwf UnilinkParity1,f
\r
568 addwf UnilinkParity1,f
\r
571 movf UnilinkParity1,w ; Carry the parity forward
\r
572 movwf UnilinkParity2M
\r
574 movf DisplayStatus,w
\r
575 addwf UnilinkParity2M,f
\r
578 addwf UnilinkParity2M,f
\r
581 addwf UnilinkParity2M,f
\r
585 movf DisplayStatus,w
\r
589 addwf UnilinkParity2M,f
\r
591 goto IRQINTParse0113Complete
\r
593 IRQINTParse0113Not80
\r
595 movf DisplayStatus,w
\r
596 xorlw 81h ; Second slave break?
\r
597 bnz IRQINTParse0113Not81
\r
599 movlw 0cdh ; Disc name
\r
600 addwf UnilinkParity1,f
\r
603 addwf UnilinkParity1,f
\r
606 movf UnilinkParity1,w ; Carry the parity forward
\r
607 movwf UnilinkParity2
\r
610 addwf UnilinkParity2,f
\r
613 addwf UnilinkParity2,f
\r
616 addwf UnilinkParity2,f
\r
619 addwf UnilinkParity2,f
\r
622 addwf UnilinkParity2,f
\r
625 addwf UnilinkParity2,f
\r
628 addwf UnilinkParity2,f
\r
631 addwf UnilinkParity2,f
\r
633 goto IRQINTParse0113Complete
\r
635 IRQINTParse0113Not81
\r
637 movf DisplayStatus,w
\r
638 xorlw 82h ; Third slave break?
\r
639 bnz IRQINTParse0113Not82
\r
641 movlw 0cdh ; Disc name
\r
642 addwf UnilinkParity1,f
\r
645 addwf UnilinkParity1,f
\r
648 movf UnilinkParity1,w ; Carry the parity forward
\r
649 movwf UnilinkParity2
\r
652 addwf UnilinkParity2,f
\r
655 addwf UnilinkParity2,f
\r
658 addwf UnilinkParity2,f
\r
661 addwf UnilinkParity2,f
\r
664 addwf UnilinkParity2,f
\r
667 addwf UnilinkParity2,f
\r
670 addwf UnilinkParity2,f
\r
673 addwf UnilinkParity2,f
\r
675 goto IRQINTParse0113Complete
\r
677 IRQINTParse0113Not82
\r
679 movf DisplayStatus,w
\r
680 xorlw 83h ; Fourth slave break?
\r
681 bnz IRQINTParse0113Not83
\r
683 movlw 0c9h ; Track name 1
\r
684 addwf UnilinkParity1,f
\r
687 addwf UnilinkParity1,f
\r
690 movf UnilinkParity1,w ; Carry the parity forward
\r
691 movwf UnilinkParity2
\r
694 addwf UnilinkParity2,f
\r
697 addwf UnilinkParity2,f
\r
700 addwf UnilinkParity2,f
\r
703 addwf UnilinkParity2,f
\r
706 addwf UnilinkParity2,f
\r
709 addwf UnilinkParity2,f
\r
712 addwf UnilinkParity2,f
\r
715 addwf UnilinkParity2,f
\r
718 goto IRQINTParse0113Complete
\r
720 IRQINTParse0113Not83
\r
722 movf DisplayStatus,w
\r
723 xorlw 84h ; Fifth slave break?
\r
724 bnz IRQINTParse0113Not84
\r
726 movlw 0c9h ; Track name (2)
\r
727 addwf UnilinkParity1,f
\r
730 addwf UnilinkParity1,f
\r
733 movf UnilinkParity1,w ; Carry the parity forward
\r
734 movwf UnilinkParity2
\r
737 addwf UnilinkParity2,f
\r
740 addwf UnilinkParity2,f
\r
743 addwf UnilinkParity2,f
\r
746 addwf UnilinkParity2,f
\r
749 addwf UnilinkParity2,f
\r
752 addwf UnilinkParity2,f
\r
755 addwf UnilinkParity2,f
\r
758 addwf UnilinkParity2,f
\r
760 goto IRQINTParse0113Complete
\r
762 IRQINTParse0113Not84
\r
764 movf DisplayStatus,w
\r
765 xorlw 85h ; Sixth slave break?
\r
766 bnz IRQINTParse0113Not85
\r
769 addwf UnilinkParity1,f
\r
772 addwf UnilinkParity1,f
\r
775 movf UnilinkParity1,w ; Carry the parity forward
\r
776 movwf UnilinkParity2M
\r
778 movf DisplayStatus,w
\r
779 addwf UnilinkParity2M,f
\r
782 addwf UnilinkParity2M,f
\r
785 addwf UnilinkParity2M,f
\r
789 movf DisplayStatus,w
\r
793 addwf UnilinkParity2M,f
\r
796 goto IRQINTParse0113Complete
\r
798 IRQINTParse0113Not85
\r
800 incf DisplayStatus,f ; Skip step one for now
\r
801 goto IRQINTParseComplete
\r
803 IRQINTParse0113Complete
\r
805 incf DisplayStatus,f ; Increment display state counter
\r
806 ; bsf DisplayStatus,7
\r
808 goto IRQINTParseBypassClear ; Don't clear the data, the buffer will be sent as the next packet
\r
812 ; Check for 01 15 (Who sent the slave break?)
\r
815 bnz IRQINTParseNot0115
\r
817 btfss DisplayStatus,7 ; First of all check if there should be anything displayed
\r
818 goto IRQINTParseComplete ; No, not at this time
\r
820 call ClearUnilinkBuffer
\r
821 movlw 10h ; Sending to Master
\r
822 addwf UnilinkParity1,f
\r
824 movlw 18h ; Broadcast address sending in this special case
\r
825 addwf UnilinkParity1,f
\r
827 movlw 82h ; Who wants to talk reply command
\r
828 addwf UnilinkParity1,f
\r
833 addwf UnilinkParity1,f
\r
836 movf UnilinkParity1,w ; Carry the parity forward
\r
837 movwf UnilinkParity2M
\r
841 addwf UnilinkParity2M,f
\r
845 addwf UnilinkParity2M,f
\r
849 addwf UnilinkParity2M,f
\r
853 addwf UnilinkParity2M,f
\r
856 goto IRQINTParseBypassClear ; Don't clear the data, the buffer will be sent as the next packet
\r
858 ;******************************************************************************
\r
859 ; Bit frig - works out which bit to set in the response to Master Poll
\r
860 ; This is taken more or less verbatim from Simon Woods' GNUnilink code!
\r
862 ; W register is input of which stage you are on (0x00, 0x20, 0x40 etc)
\r
863 ; and is returned with the byte to write (0x00 if wrong stage).
\r
866 xorwf UnilinkBit, 0
\r
867 andlw 0xe0 ; Strip off low bits
\r
869 btfsc STATUS, Z ; Do we have a hit?
\r
876 btfss UnilinkBit, 4 ; Do we need to swap nybbles?
\r
884 swapf UnilinkBit, 0
\r
892 ; Check for CMD1 = 02h (Appoint)
\r
895 bnz IRQINTParseNot02
\r
897 movf UnilinkID,w ; Do I have an ID already?
\r
898 bnz IRQINTParseComplete ; Yep, I don't want another one!
\r
900 movf UnilinkRAD,w ; So I don't have any ID yet, see what the master is trying to set
\r
901 andlw 0f0h ; Check the device group
\r
902 xorlw 0d0h ; Verify it's a MD changer
\r
903 bnz IRQINTParseComplete ; No, something else, skip this
\r
905 movf UnilinkRAD,w ; Get the ID the master has given me
\r
906 movwf UnilinkID ; Store my id
\r
907 movf UnilinkCMD2,w ; Get the bitmask
\r
908 movwf UnilinkBit ; And store it (this is needed when doing slave breaks and actually responding)
\r
910 call ClearUnilinkBuffer
\r
911 movlw 10h ; Sending to Master
\r
912 addwf UnilinkParity1,f
\r
914 movf UnilinkID,w ; This is my ID
\r
915 addwf UnilinkParity1,f
\r
917 movlw 8ch ; Device discovery command again
\r
918 addwf UnilinkParity1,f
\r
921 addwf UnilinkParity1,f
\r
924 movf UnilinkParity1,w
\r
925 movwf UnilinkParity2M ; That's the parity when sending medium messages
\r
928 addwf UnilinkParity2M,f
\r
930 movlw 0a8h ; My internal MD sends 1c here... (external/internal difference)
\r
931 addwf UnilinkParity2M,f
\r
934 addwf UnilinkParity2M,f
\r
936 movlw 0a0h ; 0a0=10disc
\r
937 addwf UnilinkParity2M,f
\r
940 bsf BUSON_OUT_BIT ; Now activate the cascade BUSON pin, to allow others after us to be discovered
\r
942 goto IRQINTParseBypassClear ; Don't clear the data, the buffer will be sent as the next packet
\r
946 ; Check for CMD1 = 80h (Display button)
\r
949 bnz IRQINTParseNot80
\r
951 movf UnilinkID,w ; Check if I'm currently selected
\r
952 xorwf UnilinkCurID,w
\r
953 skpnz ; No, skip this command
\r
954 bsf DisplayStatus,7 ; Make sure we update the display again
\r
955 goto IRQINTParseComplete
\r
959 ; Check for CMD1 = 87h (Power control)
\r
962 bnz IRQINTParseNot87
\r
964 ; This part could use some more packet sniffing (really), it's sketchy to say the least.. :(
\r
965 ; The idea here is that the 18 10 87 2a PP 12 00 80 00 PP ZZ command is sent on power-up from my headunit if green color and
\r
966 ; if amber it looks like 18 10 87 2a PP 02 00 80 00 PP ZZ, giving away that high nibble (or bit 4) of D1 sets the color
\r
967 ; Also interesting is that the exact same commands gets sent when pressing the power-off button, this makes slaves pause
\r
968 ; playing, and then a few seconds later the unit shuts down with the following command:
\r
969 ; 18 10 87 22 PP 02 00 80 00 PP ZZ or
\r
970 ; 18 10 87 22 PP 12 00 80 00 PP ZZ depending on the color of the backlight
\r
971 ; This makes me think that bit 3 in CMD2 reflects the actual power state of the headunit (actually sleeping or bus active)
\r
972 ; Anyway I use this to set/clear the RI pin used for WakeOnRing on my laptop
\r
973 ; Also I de-select to make everything pause and clear the display status (if we're doing slave breaks after power status
\r
974 ; the headunit will never enter sleep!)
\r
975 ; From what I have gathered the bit mapping of DATA1 is as follows:
\r
977 ; X - Backlight color changed if 1
\r
979 ; X - Backlight color, 0=Amber, 1=Green
\r
980 ; X - Dimmer setting changed if 1
\r
981 ; X X - Dimmer setting, 01=Dimmer Auto, 10=Dimmer On, 00=Dimmer Off, 11=???
\r
982 ; X - Beep setting, 0=Beep on(!), 1=Beep off
\r
984 ; Also bit field of CMD2 for now:
\r
986 ; X X - These two bits are set when changing color, beep etc, but now when actually powering on/off the system???
\r
987 ; X - Always set to 1 on my headunit
\r
988 ; X - Always set to 0 on my headunit
\r
989 ; X - Set to 1 when power is on, 0 when powering off (last command sent before bus dies is 87 22 on my unit)
\r
990 ; X - Always set to 0 on my headunit
\r
991 ; X - Always set to 1 on my headunit
\r
992 ; X - Always set to 0 on my headunit
\r
994 ; Test for power-on bit (it seems like bit 3 (0x08h) of CMD2 is set when the power is on)
\r
995 btfsc UnilinkCMD2,3
\r
996 goto IRQINTParse87PowerOn
\r
998 bsf RS232_RI_BIT ; Set this to make RI pin go low (after RS-232 levels)
\r
999 goto IRQINTParseComplete
\r
1001 IRQINTParse87PowerOn
\r
1002 bcf RS232_RI_BIT ; Clear this to make RI pin go high (waking the computer)
\r
1004 btfsc UnilinkCMD2,7 ; Test high bit if it's just a "set" command, if yes don't clear status
\r
1005 goto IRQINTParseComplete
\r
1007 bcf UnilinkSelected,7 ; Also de-select us (this gets sent when powering off but before the actual power down)
\r
1008 clrf DisplayStatus
\r
1010 goto IRQINTParseComplete
\r
1014 ; Check for CMD1 = 90h (Display/DSP info, volume etc.)
\r
1015 movf UnilinkCMD1,w
\r
1017 bnz IRQINTParseNot90
\r
1019 ; Check for 90 10 (Current Volume)
\r
1020 movf UnilinkCMD2,w
\r
1022 bnz IRQINTParseNot9010
\r
1024 movf UnilinkData1,w ; Store current volume setting
\r
1025 movwf UnilinkAttenuation
\r
1027 goto IRQINTParseComplete ; Don't send any reply to this (clear the packet buffer though)
\r
1029 IRQINTParseNot9010
\r
1034 ; Check for CMD1 = f0h (Source Select)
\r
1035 movf UnilinkCMD1,w
\r
1037 bnz IRQINTParseNotF0
\r
1039 movf UnilinkCMD2,w
\r
1040 movwf UnilinkCurID ; Store it for display and debugging
\r
1042 xorwf UnilinkID,w ; Check if it's selecting me
\r
1043 bnz IRQINTParseF0Deselect
\r
1045 bsf UnilinkSelected,7 ; Now we're selected
\r
1046 bsf DisplayStatus,7
\r
1047 goto IRQINTParseComplete
\r
1049 IRQINTParseF0Deselect
\r
1051 bcf UnilinkSelected,7 ; Now we're de-selected
\r
1052 bcf DisplayStatus,7
\r
1053 goto IRQINTParseComplete
\r
1057 IRQINTParseComplete
\r
1059 ; The code ends up here when parsing is complete and it's not interested in sending any reply back to the master
\r
1060 ; (that's why we clear out all the packet buffer bytes)
\r
1062 call ClearUnilinkBuffer
\r
1064 IRQINTParseBypassClear
\r
1066 movlw UnilinkRAD ; Get the pointer to the first byte in the receive buffer
\r
1067 movwf UnilinkTXRX ; Store it - this way the next byte that gets received goes into RAD
\r
1069 clrf UnilinkCmdLen ; No command length while waiting for a new packet
\r
1072 IRQINTRecvIncomplete
\r
1074 IRQINTRecvNullByte
\r
1076 ; movwf DataStore ; Store it so the non-irq code can snoop
\r
1079 bcf INTCON,INTF ; Clear the IRQ source bit to re-enable INT interrupts again
\r
1084 ;----------------------------------------------------------------
\r
1085 ; ClearUnilinkStatus - Zeroes out the Unilink state (used when initializing)
\r
1087 ClearUnilinkStatus
\r
1089 clrf UnilinkID ; Clear the existing Unilink ID, if any
\r
1090 clrf UnilinkCurID ; Clear the currently selected ID as well
\r
1091 bcf BUSON_OUT_BIT ; Clear the cascade BUSON pin, not activated again until we have a new ID
\r
1092 clrf DisplayStatus ; No crazy display updates when resetting.. :)
\r
1093 clrf UnilinkSelected ; We're not selected anymore
\r
1095 bsf STATUS,RP0 ; Reg bank 1
\r
1096 bsf DATA_BIT ; Make sure data is tristated
\r
1097 bcf STATUS,RP0 ; Reg bank 0
\r
1099 movlw UnilinkRAD ; Get the pointer to the first byte in the receive buffer
\r
1100 movwf UnilinkTXRX ; Store it - this way the next byte that gets received goes into RAD
\r
1102 clrf UnilinkCmdLen ; No command length while waiting for a new packet
\r
1104 clrf SlaveBreakState ; Slave Break Processing has to start all over
\r
1108 ;----------------------------------------------------------------
\r
1109 ; ClearUnilinkBuffer - Zeroes out the Unilink packet buffer
\r
1111 ClearUnilinkBuffer
\r
1113 ; TODO: Replace this with an FSR access to save space and make the code neater
\r
1118 clrf UnilinkParity1
\r
1128 clrf UnilinkParity2
\r
1134 subtitl "Main loop"
\r
1137 ;----------------------------------------------------------------
\r
1138 ; Main program begins here. [Called after bootloader, lcdinit and irqinit...]
\r
1139 ; Here all other house keeping tasks are performed, like displaying info on the LCD..
\r
1142 movlw high LookUp ; Set the high PC bits to indicate data lookup page
\r
1145 movlw 0ffh ; Set infinite attenuation to begin with
\r
1146 movwf UnilinkAttenuation
\r
1148 clrf UnilinkReInits ; Clear the bus re-initialization counter
\r
1150 bsf STATUS,RP0 ; Reg bank 1
\r
1151 movlw 080h ; Right adjusted A/D, all analog inputs, no Vrefs
\r
1155 movlw 081h ; Activate A/D, ch 0, Fosc/32 (for 20MHz operation)
\r
1158 bsf ADCON0,2 ; Start the first A/D operation
\r
1160 movlw 8 ; Display page timing (approx 8/sec)
\r
1161 movwf DisplayCounter
\r
1163 bcf LCD_RS_BIT ; LCD Command mode
\r
1164 movlw 80h ; DisplayRam 0
\r
1168 movlw low DefaultText1
\r
1172 call TxLCD8BLoop ; Send 80 bytes to the LCD
\r
1176 bcf LCD_RS_BIT ; LCD Command mode
\r
1177 movlw 80h ; DisplayRam 0
\r
1182 movf Counter,w ; Debug timer
\r
1183 btfsc PORTA,4 ; Test RST
\r
1188 movf SlaveBreakState,w
\r
1190 btfsc PORTB,0 ; Test CLK
\r
1195 btfsc PORTC,2 ; Test BUSON-IN
\r
1200 btfsc PORTC,3 ; Test DATA
\r
1204 movf UnilinkCmdLen,w
\r
1205 bz MainDontPrintCmd
\r
1212 ; UnilinkID @ 13-14
\r
1213 ; UnilinkAttenuation @ 16-17
\r
1214 ; UnilinkSelected @ 28-29
\r
1215 ; UnilinkReInits @ 38,39
\r
1216 ; UnilinkCurID @ 54-55
\r
1217 ; DisplayStatus @ 62-63
\r
1218 ; BattVoltage @ 66,67,69,70 (thou,hund,tens,unit)
\r
1220 bcf LCD_RS_BIT ; LCD Command mode
\r
1221 movlw 80h+13 ; DisplayRam 13
\r
1228 bcf LCD_RS_BIT ; LCD Command mode
\r
1229 movlw 80h+16 ; DisplayRam 16
\r
1233 movf UnilinkAttenuation,w
\r
1236 bcf LCD_RS_BIT ; LCD Command mode
\r
1237 movlw 80h+28 ; DisplayRam 28
\r
1241 movf UnilinkSelected,w
\r
1244 bcf LCD_RS_BIT ; LCD Command mode
\r
1245 movlw 80h+38 ; DisplayRam 38
\r
1249 movf UnilinkReInits,w
\r
1252 bcf LCD_RS_BIT ; LCD Command mode
\r
1253 movlw 80h+40h+14 ; DisplayRam 54
\r
1257 movf UnilinkCurID,w
\r
1260 bcf LCD_RS_BIT ; LCD Command mode
\r
1261 movlw 80h+40h+22 ; DisplayRam 62
\r
1265 movf DisplayStatus,w
\r
1268 btfsc ADCON0,2 ; Test if A/D is ready
\r
1269 goto MainADNotReady
\r
1272 movf ADRESL,w ; Add to our result
\r
1278 addwf NumH,f ; And the high byte
\r
1282 skpc ; When this overflows we know there are 8 samples collected
\r
1283 goto MainADStartAD
\r
1285 ; Now shift the added results two steps down (/4) as there are 8 added samples here, and filter high bits
\r
1296 bnz MainADSkipDisplay
\r
1298 bcf LCD_RS_BIT ; LCD Command mode
\r
1299 movlw 80h+40h+26 ; DisplayRam 66
\r
1325 bsf ADCON0,2 ; Start a new conversion
\r
1329 ; This part handles display "scroll" by shifting one screen at a time
\r
1331 btfss Counter,7 ; Test high bit
\r
1332 goto MainCounterLow
\r
1334 ; So bit is high, set high bit of displaycounter as well...
\r
1335 bsf DisplayCounter,7
\r
1336 goto MainSkipScroll
\r
1339 ; OK, bit is low, now figure out whether it was high or low last time -> check high bit of DisplayCounter
\r
1340 btfss DisplayCounter,7
\r
1341 goto MainSkipScroll
\r
1343 bcf DisplayCounter,7 ; Clear the high bit to allow countdown to commence
\r
1344 movf Counter,w ; Load it
\r
1346 goto MainSkipScroll
\r
1347 decfsz DisplayCounter,f
\r
1348 goto MainSkipScroll
\r
1351 movwf DisplayCounter
\r
1353 bcf LCD_RS_BIT ; LCD Command mode
\r
1354 movlw 18h ; Display shift Left
\r
1355 call TxLCDB ; Shift it 8 positions
\r
1367 ; Display scroll part ends here...
\r
1372 ;----------------------------------------------------------------
\r
1373 ; IRQInit - Sets up the IRQ Handler
\r
1374 ; Set up Timer2 to generate 2000 interrupts per second, used for timing - 1/16 prescaler and a PR2 reg of 156 (0x9c) is set
\r
1375 ; Also enable INT interrupts for Unilink CLK processing
\r
1379 call ClearUnilinkStatus
\r
1380 call ClearUnilinkBuffer
\r
1382 ; Fix the output state of RI and BUSON_OUT to a safe default
\r
1384 bsf RS232_RI_BIT ; RS232 RI should be inactive (inverted logic, a set bit here gives a negative output)
\r
1385 bcf BUSON_OUT_BIT ; BUSON_OUT should be disabled for now, must be appointed first
\r
1387 movlw 06h ; Timer2 enabled + 1/16 prescaler
\r
1390 bsf STATUS,RP0 ; Reg bank 1
\r
1392 movlw 09ch ; Timer PR2 reg giving 2000 interrupts per second
\r
1395 bcf RS232_RI_BIT ; Both bits should be outputs
\r
1396 bcf BUSON_OUT_BIT ;
\r
1398 ; The default behavior of RB0/INT is to interrupt on the rising edge, that's what we use...
\r
1399 ; bcf OPTION_REG,INTEDG ; We want RB0 to give us an IRQ on the falling edge
\r
1401 bsf INTCON,INTE ; Enable the RB0/INT
\r
1402 bsf INTCON,PEIE ; Enable the peripheral interrupts
\r
1403 bsf PIE1,TMR2IE ; Enable the Timer2 peripheral interrupt
\r
1404 bsf INTCON,GIE ; Enable global interrupts
\r
1406 bsf TXSTA,TXEN ; Enable UART TX
\r
1408 bcf STATUS,RP0 ; Back to bank 0
\r
1410 bsf RCSTA,SPEN ; Enable serial port
\r
1411 bsf RCSTA,CREN ; Enable UART RX
\r
1415 ;----------------------------------------------------------------
\r
1416 ; Initialize LCD Controller...
\r
1419 clrf PORTB ; First clear PortB data register
\r
1420 bsf STATUS,RP0 ; Reg bank 1
\r
1421 movlw 001h ; All but RB0 are outputs.
\r
1424 bcf OPTION_REG,NOT_RBPU ; Turn on port B pull-up
\r
1425 bcf STATUS,RP0 ; Restore Reg bank 0
\r
1427 ; This is a standard reset sequence for the LCD controller
\r
1429 movlw 170 ; Need to delay for at least 15ms, let's go for 17ms delay
\r
1432 movlw 3 ; Write 3 to the LCD
\r
1433 call TxLCD ; Send to LCD
\r
1434 movlw 60 ; Need to delay for at least 4.1ms, let's go for 6ms delay
\r
1437 movlw 3 ; Write 3 to the LCD
\r
1439 movlw 10 ; Need to delay for at least 100us, let's go for 1ms delay
\r
1442 movlw 3 ; Write 3 to the LCD
\r
1444 movlw 10 ; Need to delay for at least 40us, let's go for 1ms delay
\r
1447 movlw 2 ; 4-bit interface requested
\r
1449 movlw 10 ; Need to delay for at least 40us, let's go for 1ms delay
\r
1452 ; Reset sequence ends here
\r
1453 ; From this point no delays are needed, now the BUSY bit is valid and the bus I/F is 4 bits
\r
1455 movlw 28h ; Function Select + 4-bit bus + 2-line display
\r
1458 movlw 0ch ; Display Control + LCD On (No cursor)
\r
1461 movlw 01h ; Clear Display
\r
1464 movlw 06h ; Auto Increment cursor position
\r
1467 bsf LCD_RS_BIT ; Accept data
\r
1471 ;----------------------------------------------------------------
\r
1473 ; Sends two characters hex to the LCD
\r
1477 ; Original binary to 2-digit hex conversion from piclist.com, modified to fit here
\r
1507 ;----------------------------------------------------------------
\r
1509 ; Binary-to-BCD. Written by John Payson.
\r
1510 ; Taken from piclist.com - why re-invent the wheel when writing open-sourced code?
\r
1512 ; Enter with 16-bit binary number in NumH:NumL.
\r
1513 ; Exits with BCD equivalent in TenK:Thou:Hund:Tens:Ones.
\r
1516 BCDConvert: ; Takes number in NumH:NumL
\r
1517 ; Returns decimal in
\r
1518 ; TenK:Thou:Hund:Tens:Ones
\r
1520 andlw 0Fh ;*** PERSONALLY, I'D REPLACE THESE 2
\r
1521 addlw 0F0h ;*** LINES WITH "IORLW 11110000B" -AW
\r
1557 ; At this point, the original number is
\r
1558 ; equal to TenK*10000+Thou*1000+Hund*100+Tens*10+Ones
\r
1559 ; if those entities are regarded as two's compliment
\r
1560 ; binary. To be precise, all of them are negative
\r
1561 ; except TenK. Now the number needs to be normal-
\r
1562 ; ized, but this can all be done with simple byte
\r
1589 ;----------------------------------------------------------------
\r
1591 ; Send a string to the LCD.
\r
1596 movlw 80h ; DisplayRam 0
\r
1601 movlw 80h+40 ; DisplayRam 40 (row 2)
\r
1607 ;----------------------------------------------------------------
\r
1609 ; Send a string to the LCD.
\r
1612 ; movwf Icount ; Icount = W
\r
1614 movwf e_LEN ; Move to e_LEN
\r
1617 movf Icount,w ; get the byte
\r
1619 incf Icount,f ; ...else ++Icount (table index)
\r
1620 call TxLCDB ; Send out the byte
\r
1625 ;----------------------------------------------------------------
\r
1626 ; TxLCDB - send a byte to the LCD
\r
1629 movwf TxTemp ; Store byte to send for a while...
\r
1631 bcf temp,0 ; Clear my temp bit
\r
1632 btfss LCD_RS_BIT ; Check if we try the correct reg
\r
1635 bsf temp,0 ; Indicate RS change
\r
1639 call RxLCDB ; Receive byte from LCD, status reg
\r
1641 skpz ; If the bit was set, the zero flag is not
\r
1644 btfsc temp,0 ; If we had to clear RS reset it now
\r
1647 swapf TxTemp,w ; Hi nibble of data to send in lo w bits
\r
1648 call TxLCD ; Send them first...
\r
1649 movf TxTemp,w ; Then we have the low nibble in low w bits
\r
1650 call TxLCD ; And send that one as well
\r
1654 ;----------------------------------------------------------------
\r
1655 ; RxLCDB - recv a byte from the LCD
\r
1658 call RxLCD ; Receive the high nibble
\r
1660 swapf LCDWTmp,f ; Swap it back to file
\r
1661 call RxLCD ; Receive the low nibble
\r
1662 addwf LCDWTmp,w ; Put the nibbles together and return in W
\r
1666 ;----------------------------------------------------------------
\r
1667 ; TxLCD - send a nibble to the LCD
\r
1670 movwf LCDWTmp ; Write nibble to tmp
\r
1671 bcf LCD_DB4_BIT ; Clear previous data
\r
1672 bcf LCD_DB5_BIT ;
\r
1676 btfsc LCDWTmp,0 ; Test bit 0, transfer a set bit to LCD PORT
\r
1678 btfsc LCDWTmp,1 ; Test bit 1, transfer a set bit to LCD PORT
\r
1680 btfsc LCDWTmp,2 ; Test bit 2, transfer a set bit to LCD PORT
\r
1682 btfsc LCDWTmp,3 ; Test bit 3, transfer a set bit to LCD PORT
\r
1685 bsf LCD_E_BIT ; And set E to clock the data into the LCD module
\r
1686 nop ; Let it settle
\r
1687 bcf LCD_E_BIT ; And clear the Enable again.
\r
1688 return ; Returns without modifying W
\r
1690 ;----------------------------------------------------------------
\r
1691 ; RxLCD - recv a nibble from the LCD
\r
1694 clrw ; Clear W register, return data in lower 4 bits
\r
1696 bsf STATUS,RP0 ; Select 2nd reg bank, now TRIS regs can be accessed
\r
1698 bsf LCD_DB4_BIT ; This sets the port bit as an input
\r
1703 bcf STATUS,RP0 ; Back at reg bank 0
\r
1705 bsf LCD_RW_BIT ; Set Read mode for the LCD
\r
1706 bsf LCD_E_BIT ; And set E to clock the data out of the LCD module
\r
1707 nop ; Let the bus settle
\r
1708 btfsc LCD_DB4_BIT ; Transfer a set port bit into W
\r
1710 btfsc LCD_DB5_BIT ; Transfer a set port bit into W
\r
1712 btfsc LCD_DB6_BIT ; Transfer a set port bit into W
\r
1714 btfsc LCD_DB7_BIT ; Transfer a set port bit into W
\r
1716 bcf LCD_E_BIT ; And clear the Enable again.
\r
1717 bcf LCD_RW_BIT ; Set Write mode for the LCD
\r
1719 bsf STATUS,RP0 ; Select 2nd reg bank, now TRIS regs can be accessed
\r
1721 bcf LCD_DB4_BIT ; Set the port as an output again
\r
1722 bcf LCD_DB5_BIT ;
\r
1726 bcf STATUS,RP0 ; Back at reg bank 0
\r
1728 return ; Returns with data in W
\r
1730 ;----------------------------------------------------------------------
\r
1731 ; Delay routines (non-interrupt based, therefore not even close to reliable)
\r
1732 ; W=10 gives ~ 1ms of delay
\r
1733 ; 1ms=5000 instructions wasted, 100us=500 cycles
\r
1734 ; Maximum time waited will be 256*100us=25.6ms
\r
1737 movwf Dcount ; Set delay counter, number of 100us periods to wait
\r
1740 movlw 0a5h ; This gives 165 iterations of the inner loop, wastes 495 cycles + these two + one more
\r
1741 movwf Dcount2 ; exiting the loop + 3 more for the outer loop = 501 cycles for every Dcount
\r
1743 decfsz Dcount2,f ; 1 cycle (or two when exiting the loop)
\r
1744 goto DelayInner ; 2 cycles
\r
1745 decfsz Dcount,f ; Now decrement number of 100us periods and loop again
\r
1750 ;----------------------------------------------------------------
\r
1751 ; Data can be stored between 600 and 6ffh...
\r
1756 ; UnilinkID @ 13-14
\r
1757 ; UnilinkAttenuation @ 16-17
\r
1758 ; UnilinkSelected @ 28-29
\r
1759 ; UnilinkReInits @ 38,39
\r
1760 ; UnilinkCurID @ 54-55
\r
1761 ; DisplayStatus @ 62-63
\r
1762 ; BattVoltage @ 66,67,69,70 (thou,hund,tens,unit)
\r
1765 DT "----- WJ", "MyID:xx ", "xx dB at", "Sel:xx B", "Inits:xx"
\r
1766 DT " Unilink", "CurID:xx", "t Dsp:xx", "atxx.xxV", " <WJ>"
\r
1775 DT "..",0,0,0,0,0,0
\r
1777 LookUp movwf PCL ; Go to it (this assumes PCLATH == 06h)
\r
1780 subtitl "Bootstrap/Bootloader code"
\r
1783 ;----------------------------------------------------------------------
\r
1784 ; Bootstrap code - Allows PIC to flash itself with data from the async port.
\r
1785 ; Accepts a standard INHX8 encoded file as input, the only caveat is that the code is slow when writing to memory
\r
1786 ; (we have to wait for the flash to complete), and therefore care has to be taken not to overflow the RS232 receiver
\r
1787 ; (one good way of solving that is to wait for the echo from the PIC before sending anything else)
\r
1788 ; Both program memory and Data EEPROM memory can be programmed, but due to hardware contraints the configuration
\r
1789 ; register can't be programmed. That means that any references to the config register in the hex file will be ignored.
\r
1791 ; Startup @9600bps
\r
1793 ; RAM usage for the bootstrap code
\r
1795 BootBits equ 7eh ; bit0 1=write 0=read, bit1 1=PGM 0=EE, bit2 0=normal 1=no-op when prog
\r
1800 BootTimerL equ 79h
\r
1801 BootTimerM equ 78h
\r
1802 BootTimerH equ 77h
\r
1803 BootNumBytes equ 76h
\r
1804 BootDataVL equ 75h
\r
1805 BootDataVH equ 74h
\r
1806 BootHEXTemp equ 73h
\r
1808 org 738h ; Place the boot code at the top of memory (currently the loader is exactly 200 bytes)
\r
1811 bsf STATUS,RP0 ; Access bank 1
\r
1812 bsf TXSTA,TXEN ; Enable UART TX
\r
1813 movlw 31 ; Divisor for 9k6 @ 20MHz Fosc
\r
1814 movwf SPBRG ; Store
\r
1815 bcf STATUS,RP0 ; Back to bank 0
\r
1817 bsf RCSTA,SPEN ; Enable serial port
\r
1818 bsf RCSTA,CREN ; Enable UART RX
\r
1820 movlw low BootStartText ; Send boot banner to the serial port
\r
1823 ; movlw 0e8h ; Initialize timeout timer (e8 is about 3 secs)
\r
1824 movlw 0fdh ; Initialize timeout timer (fd is short enough to get the headunit to recognize us)
\r
1830 incf BootTimerL,f ; A 24-bit counter
\r
1835 skpnz ; When overflowing here..
\r
1836 goto BootReturn ; ..Exit boot loader, no keypress within timeout period, resume program
\r
1837 btfss PIR1,RCIF ; Wait for RX to complete
\r
1842 goto BootTimeout ; If it wasn't ESC, wait for another key
\r
1845 movlw low BootFlashText ; OK, flashing it is, send "start" text to serial port
\r
1853 call BootRXB ; First find the ':'
\r
1856 goto BootLoop ; Loop until we find it!
\r
1858 call BootRXHEX ; Get one ASCII encoded byte (two chars)
\r
1859 movwf BootNumBytes ; This is the number of bytes to be programmed on the line
\r
1860 ; Maybe clear cary here?
\r
1861 rrf BootNumBytes,f ; Right shift because we're double addressing this 8-bit format
\r
1863 ; Note carry should be clear here as there cannot be odd number of bytes in this format
\r
1865 call BootRXHEX ; Receive AddrH
\r
1867 call BootRXHEX ; Receive AddrL
\r
1869 rrf BootAddrH,f ; Fix the addressing again
\r
1872 bcf BootBits,2 ; Assume we should program
\r
1873 bsf BootBits,1 ; And assume we should program flash not ee
\r
1876 xorlw 020h ; Check if it's configuration, which we can't program
\r
1877 skpnz ; Skip the bit set if it was false alarm
\r
1878 bsf BootBits,2 ; No programming for this line
\r
1880 xorlw 001h ; Also check if it's EEPROM memory (first xor 20h then 1 =21h)
\r
1881 skpnz ; Skip the bit set instr if not EE data address
\r
1882 bcf BootBits,1 ; We should program EE, will ignore the AddrH
\r
1884 call BootRXHEX ; Receive Record Type (must be 0 for real records)
\r
1885 skpz ; Check if zero
\r
1886 goto BootFlashComplete
\r
1889 call BootRXHEX ; Receive low-byte of data word
\r
1891 call BootRXHEX ; Receive high-byte of data word
\r
1894 btfsc BootBits,2 ; Check whether this line should be programmed at all
\r
1895 goto BootWriteSkip
\r
1897 bcf BootBits,0 ; Read mode first, verify if we actually have to write
\r
1900 xorwf BootDataL,f ; Compare and destroy DataL
\r
1901 movwf BootDataL ; Write new data to DataL
\r
1902 skpz ; Skip if no difference, have to check high byte as well
\r
1903 goto BootWrite ; Jump directly to write
\r
1906 xorwf BootDataH,f ; Compare
\r
1907 skpnz ; Skip if no difference, no programming necessary
\r
1908 goto BootWriteSkip
\r
1912 movwf BootDataH ; Have to put the new H byte data in as well
\r
1915 call BootEE ; Write directly into program mem
\r
1917 ; Here a verify can take place, the read-back results are now in DataL/H
\r
1921 incf BootAddrL,f ; Advance counter to next addr
\r
1923 incf BootAddrH,f ; And add to high byte if needed
\r
1925 decfsz BootNumBytes,f
\r
1933 movlw low BootRunText
\r
1936 bsf STATUS,RP0 ; Reg bank 1
\r
1938 btfss TXSTA,TRMT ; Wait for last things to flush
\r
1939 goto BootReturnWait
\r
1940 bcf TXSTA,TXEN ; Disable UART TX
\r
1941 bcf STATUS,RP0 ; Back to bank 0
\r
1943 bcf RCSTA,SPEN ; Disable serial port
\r
1944 bcf RCSTA,CREN ; Disable UART RX
\r
1946 return ; Return to code
\r
1948 ;----------------------------------------------------------------------
\r
1949 ; BootTXB - Sends one byte to the UART, waits for transmitter to become
\r
1950 ; free before sending
\r
1954 btfss PIR1,TXIF ; Wait for TX to empty
\r
1956 movwf TXREG ; Send the byte
\r
1959 ;----------------------------------------------------------------------
\r
1960 ; BootTXStr - Sends ASCII string pointed to by W, zero terminated
\r
1963 movwf BootAddrL ; Store LSB of text pointer
\r
1964 movlw 07h ; MSB of pointer to the text (0700h in this boot loader)
\r
1966 movlw 02h ; Select "Read Program Memory" operation
\r
1969 call BootEE ; Lookup char (actually two packed into one word)
\r
1970 rlf BootDataL,w ; Shift the MSB out into carry (that's the 2nd char LSB)
\r
1971 rlf BootDataH,w ; Shift it into 2nd char
\r
1972 call BootTXB ; Send the high byte first
\r
1973 movf BootDataL,w ; Get the low byte
\r
1974 andlw 07fh ; Mask of the highest bit
\r
1975 skpnz ; Stop if zero
\r
1977 call BootTXB ; Send char
\r
1978 incf BootAddrL,f ; Increment pointer
\r
1979 goto BootTXStrLoop
\r
1981 ;----------------------------------------------------------------------
\r
1982 ; BootRXB - Receives one byte from the UART, waits if nothing available
\r
1986 btfss PIR1,RCIF ; Wait for RX to complete
\r
1988 movf RCREG,w ; Get the recvd byte
\r
1989 call BootTXB ; Echo to terminal
\r
1992 ;----------------------------------------------------------------------
\r
1993 ; BootRXHEXNibble - Receives one byte and converts it from ASCII HEX to binary
\r
1996 call BootRXB ; Receive nibble
\r
1998 ; This code is from piclist.com, really neat!
\r
2000 addlw -'A' ; Convert from BCD to binary nibble
\r
2001 skpc ; Test if if was 0-9 or A-F, skip if A-F
\r
2002 addlw 'A' - 10 - '0' ; It was numeric '0'
\r
2003 addlw 10 ; Add 10 (A get to be 0ah etc.)
\r
2007 ;----------------------------------------------------------------------
\r
2008 ; BootRXHEX - Receives two bytes from the UART, waits if nothing available
\r
2009 ; Decodes the bytes as ASCII hex and returns a single byte in W
\r
2012 call BootRXHEXNibble
\r
2014 swapf BootHEXTemp,f ; Swap it up to the high nibble
\r
2016 call BootRXHEXNibble
\r
2017 addwf BootHEXTemp,w ; And add the two nibbles together
\r
2020 ;----------------------------------------------------------------------
\r
2021 ; BootEE - Reads or writes EE or Flash memory, BootBits specify the
\r
2022 ; exact action to take. BootAddrL and BootAddrH has to be initialized
\r
2023 ; to the address of choice (0000-003fh for EE and 0000h-07ffh for flash
\r
2024 ; The data to be written has to be put in BootDataL and BootDataH, and
\r
2025 ; data will be to the same place when read back
\r
2028 bsf STATUS,RP1 ; Select bank 2 (RP0 must be 0)
\r
2030 movf BootAddrH,w ; Load desired address
\r
2034 movf BootDataH,w ; And load the data (only used when writing)
\r
2039 bsf STATUS,RP0 ; Go to bank 3
\r
2041 bsf EECON1,EEPGD ; Point to Program Flash mem
\r
2042 btfss BootBits,1 ; Test if that was correct or if we have to clear again
\r
2043 bcf EECON1,EEPGD ; Point to EE DATA mem
\r
2045 btfss BootBits,0 ; Check from read or write
\r
2046 goto BootEERD ; Skip the WR if we were going for a read
\r
2048 bsf EECON1,WREN ; Enable writes
\r
2052 movwf EECON2 ; Unlock write operation
\r
2053 bsf EECON1,WR ; And start a write cycle
\r
2055 btfsc EECON1,WR ; This executes for EE only not flash, waits for WR to finish
\r
2056 goto BootWRLoop ; These two instructions gets NOPed when flashing
\r
2058 bcf EECON1,WREN ; Finally disable writes again
\r
2059 ; Here we read the data back again, can be used as verify
\r
2061 bsf EECON1,RD ; Start a read cycle
\r
2062 nop ; Only necessary for flash read, same thing as when writing above
\r
2063 nop ; Except I could use the two words for something useful there.. :)
\r
2066 bcf STATUS,RP0 ; Back to bank 2
\r
2067 movf EEDATA,w ; Store our EE-data
\r
2071 bcf STATUS,RP1 ; And finally back to bank 0
\r
2075 ; To produce compact code the end zero byte has to be in the LSB (that means an even number of chars in every string)
\r
2077 DA "WJBoot - press ESC to flash\x00"
\r
2080 DA "\r\nSend INHX8 file now...\r\x00"
\r
2083 DA "\r\nExiting loader\r\x00"
\r
2085 ;----------------------------------------------------------------------
\r
2086 ; EE Data (64 bytes), located at 2100h
\r
2089 ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
\r
2090 ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
\r
2091 ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
\r
2092 ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
\r
2093 ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
\r
2094 ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
\r
2095 ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
\r
2096 ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh
\r