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(parent: 2917ec4) | patch
v0.7 - Debug Serial TX in ISR now, checksum check for incoming packets in place,...
authorWerner Johansson <wj@xnk.nu>
Sun, 9 Mar 2003 23:19:40 +0000 (15:19 -0800)
committerWerner Johansson <wj@xnk.nu>
Sun, 17 Oct 2010 00:35:09 +0000 (17:35 -0700)
commit68e0b7acbba32b2b6786ce364128377fae40572f
tree4db36fe53f09975766ecb20e10c91805a2543a0dtree | snapshot
parent2917ec4990958da6e4c5a5016132fe90a26c938bcommit | diff
v0.7 - Debug Serial TX in ISR now, checksum check for incoming packets in place, A/D works, solved the master reset prob

(by calling the INT handler from TMR2 ISR code (too much interrupt latency when transmitting)

Signed-off-by: Werner Johansson <wj@xnk.nu>
wj-uni.asm diff | blob | history
PIC16F870-based Unilink (R) interface