title "PIC16F870 Unilink(R) Interface by Werner Johansson (c) 2003" subtitl "Definitions" list c=150,P=16F870,R=DEC,F=inhx8m include "p16f870.inc" ; Standard equates & Macros ERRORLEVEL 1,-302 ; Get rid of those annoying 302 msgs! ;---------------------------------------------------------------- ; The Configuration Word __CONFIG _HS_OSC&_WDT_OFF&_PWRTE_ON&_BODEN_ON&_LVP_OFF&_CPD_OFF&_WRT_ENABLE_ON&_DEBUG_OFF&_CP_OFF ;---------------------------------------------------------------- ; TODO ;---------------------------------------------------------------- ; Fix the DelayW routine so it actually delays W/10 ms... ; No checksum checking is done on incoming packets ; Investigate whether I actually have to save PCLATH in ISH, maybe save FSR? ; Move RS232 code into ISH ; Check Overrun errors from the UART ; Implement lots of other Unilink commands (Text display, time display etc.) ; Implement the Watchdog Timer (might be useful even though I haven't seen it hang yet..) ;---------------------------------------------------------------- ; HISTORY ;---------------------------------------------------------------- ; Version ; ; 0.4 Some fixups in the bootstrap code (I actually had to put the PIC in my PICSTART Plus programmer again :)) ; 0.3 Implementing more Unilink commands and RingIndicator control (to wake the computer from sleep) ; 0.2 First attempt at responding to the Anyone command ; 0.1 Receives Unilink data OK, relays it to serial ; 0.0 Very first "F**king No Work!" version ;---------------------------------------------------------------- ; I/O LAYOUT ;---------------------------------------------------------------- ; Unilink BUSON IN (blue) connected to RC2/CCP1 ; Unilink DATA (green) connected to RC3 ; Unilink BUSON OUT (blue) connected to RC4 (this is for daisy-chaining) ; Unilink CLK (yellow) connected to RB0/INT (Interrupt pin) ; Unilink RST (lilac) connected to RA4 ; LCD RS connected to pin RB1 (The LCD is a standard 16x1 char HD44780 compatible unit) ; LCD RW connected to pin RB2 ; LCD E connected to pin RB3 ; LCD DB4-DB7 connected to RB4-RB7 ; RS-232 TX from computer connected to RC7/RX ; RS-232 RX to computer connected to RC6/TX ; RS-232 RI to computer connected to RC5 ; ; This leaves RC0, RC1 and the analog inputs (AN0-AN4) free for now... #define BUSON_IN_BIT PORTC,2 #define DATA_BIT PORTC,3 #define BUSON_OUT_BIT PORTC,4 #define CLK_BIT PORTB,0 #define RST_BIT PORTA,4 #define LCD_RS_BIT PORTB,1 #define LCD_RW_BIT PORTB,2 #define LCD_E_BIT PORTB,3 #define LCD_DB4_BIT PORTB,4 #define LCD_DB5_BIT PORTB,5 #define LCD_DB6_BIT PORTB,6 #define LCD_DB7_BIT PORTB,7 #define RS232_RI_BIT PORTC,5 ;---------------------------------------------------------------- ; FILE REGISTER USAGE ;---------------------------------------------------------------- Dcount equ 20h e_LEN equ 21h Counter equ 22h SlaveBreakState equ 23h ; Hold state and time-out information about slave break, indicates when it can happen Icount equ 2Dh ; Offset of string to print TxTemp equ 2Eh ; blahblah TxTemp2 equ 2Fh ; Blahblah2 LCDWTmp equ 30h Dcount2 equ 31h temp equ 32h DataCount equ 33h ; Temp storage for the bit counter used during bit shifts (Unilink TX/RX) DataStore equ 34h ; This is a kludge UnilinkSelected equ 3bh UnilinkBit equ 3ch ; This is my "bitmask" to be used for requests UnilinkID equ 3dh ; This is my Bus ID UnilinkCmdLen equ 3eh ; This gets updated with the actual packet length after CMD1 has been received UnilinkTXRX equ 3fh ; This is a pointer to the Unilink packet below, used with indirect addressing UnilinkRAD equ 40h ; Beginning of Unilink packet - the Receiving Address UnilinkTAD equ 41h ; Transmitter address UnilinkCMD1 equ 42h ; CMD1 byte UnilinkCMD2 equ 43h ; CMD2 byte UnilinkParity1 equ 44h ; First or only parity byte for short packets (6 bytes) UnilinkData1 equ 45h ; Extra data for medium/large packets, or zero for short packets UnilinkData2 equ 46h ; UnilinkData3 equ 47h ; UnilinkData4 equ 48h ; UnilinkData5 equ 49h ; Data5 if this is a large packet UnilinkParity2M equ 49h ; Parity2 shares the same byte if it's a medium sized packet UnilinkData6 equ 4ah ; Extra data for large packets, or zero for medium packets UnilinkData7 equ 4bh ; UnilinkData8 equ 4ch ; UnilinkData9 equ 4dh ; UnilinkParity2 equ 4eh ; Parity byte for large packets UnilinkZero equ 4fh ; Should always be zero (possibly used to signal corrupt packets from slave to master?) IRQPCLATH equ 7dh ; ISH storage IRQSTATUS equ 7eh ; Needs to be located in a shared area accessible from all register banks IRQW equ 7fh ; subtitl "Startup" page ;---------------------------------------------------------------- ; Power up/Reset starting point org 0 ; Start at the beginning of memory (the reset vector) call Bootstrap ; Call Flash Load routine call LCDInit ; Initialize LCD I/F call IRQInit ; Set up and start the IRQ handler goto Main ; Run the main program loop (skip the IRQ handler) subtitl "IRQ Handler" ;---------------------------------------------------------------- ; Interrupt handler always starts at addr 4 ; In order to reduce the INT latency the actual code is put here directly instead of using a goto instruction. ; Also because of the real-time requirements for clocking data onto the Unilink bus the first check in the ISR ; is to see whether the Unilink clock rise was the reason for the interrupt. This results in a "clock rise to ; bit ready" time of less than 30 instruction cycles, should be plenty of spare time waiting for clock to go low ; again after that. Other interrupts might introduce latencies, but let's see how this works.. org 4 ; ISR vector is at address 4 movwf IRQW ; Save W swapf STATUS,w ; Get the status register into w clrf STATUS ; Zero out the status reg, gives Reg Bank0 movwf IRQSTATUS ; Store the STATUS reg movf PCLATH,w ; Get the PCLATH reg ; movwf IRQPCLATH ; And store it ; clrf PCLATH ; Go to low memory ; Maybe save FSR here as well (if there's a need for it in the non-ISR code) btfss INTCON,INTF ; Check if it's the INT edge interrupt (Unilink CLK) goto IRQNotINT ; No it's not, check the other sources ; If there's activity on the clock line (the clock goes high) the CPU will stay in here until eight bits have been clocked in ; - this reduces context switching (and it's just a few hundred cpu cycles after all (20us*8 bits=160us=800 instruction ; cycles (5 MIPS @ 20MHz), not even a problem for serial input if it's not receiving more than 6250 bytes per second, and the ; 2-byte FIFO somehow fills up (this should be impossible even @ 115200 as this blocking INT handler only runs a maximum of ; 1000 times per second, halting INT's for 1/6250 of a second - this gives the CPU ample of time to deal with all bytes from ; the USART. I should check the OERR (Serial Overrun) bit to catch this though.. Note that this piece of code does both TX ; and RX at the same time (in order to receive packets one has to make sure that the packet buffer is zeroed out before entering ; here, otherwise collisions will occur.. ; According to my logic analyzer this implementation is pretty decent when it comes to timing, even though it's an ; interrupt driven "USART" implemented in software - by trigging the interrupt on the rising edge there's some extra margin here ; (the clock goes high 10us before the master clocks the bit in (on the falling edge), that should be plenty of time..) movlw 8 ; Loop through the 8 bits movwf DataCount movf UnilinkTXRX,w ; Get the pointer movwf FSR ; Store it to make use of indirect addressing IRQINTBitSet btfss INDF,7 ; Test high bit of data (that's the first bit to be clocked out) goto IRQINTTristate ; Bit is low, we should tristate bit bcf PORTC,3 ; Otherwise set DATA bit low bsf STATUS,RP0 ; Select high regs bcf TRISC,3 ; And pull low (now it's an output) bcf STATUS,RP0 ; Back to regbank 0 goto IRQINTCLKWaitLow ; Wait for master to actually clock this bit in IRQINTTristate bsf STATUS,RP0 ; Select high regs bsf TRISC,3 ; Force the bit to be tristated bcf STATUS,RP0 ; Back to regbank 0 IRQINTCLKWaitLow btfss PORTC,2 ; Check for BUSON goto IRQAfterINT btfsc PORTB,0 ; Wait for clock to go low goto IRQINTCLKWaitLow clrc ; Clear carry btfss PORTC,3 ; Test DATA setc ; Set carry if data is LOW (data is inverted!) rlf INDF,f ; Shift it into the "accumulator" decfsz DataCount,f ; Loop once more perhaps? goto IRQINTCLKWaitHigh ; Yes, again! goto IRQINTRecvDone ; No it's done, don't check for clock to go high again IRQINTCLKWaitHigh btfss PORTC,2 ; Check for BUSON goto IRQAfterINT btfss PORTB,0 ; Wait for clock to go high goto IRQINTCLKWaitHigh goto IRQINTBitSet ; Loop again ; Successfully received a byte here, run it through a state machine to figure out what to do ; (several possibilites exists here): ;;;;;; If more than 1.1ms has passed since last receive, reset receive counter to zero ; If receive counter is zero and the received byte is a zero byte, discard it ; Otherwise store the byte in our receive buffer and increment receive counter ; If the receive counter is 3 check the two upper bits of recv'd byte (CMD1) - this tells us the length of the packet ; 00 = short 6 byte packet ; 10 = medium 11 byte packet ; 11 = long 16 byte packet ; Update the receive length byte accordingly ; Check whether receive length and receive count are equal, that means that we're finished and we can carry on parsing ; the packet and take appropriate action. IRQINTRecvDone clrf SlaveBreakState ; First of all, clear the break state - this got in the way, restart detection.. movf UnilinkTXRX,w ; Find out which byte # that was received andlw 0fh ; Mask bnz IRQINTRecvNotFirst ; Not the first byte movf UnilinkRAD,w ; Get the first byte received bz IRQINTRecvNullByte ; Null byte received, ignore this, don't increment counter IRQINTRecvNotFirst incf UnilinkTXRX,f ; Increment address movf UnilinkTXRX,w ; Get the byte position again andlw 0fh ; Only lower 4 bits of interest xorlw 03h ; Well, is it the third byte? (CMD1, telling us the length of the packet) bnz IRQINTRecvNotCMD1 ; No, skip the length code for now movlw 6 ; Assume it's a short packet btfss INDF,7 ; INDF still points to received byte, test high bit for medium/long goto IRQINTRecvShort ; Nope, it's a short packet addlw 5 ; OK, it's long or medium at least btfsc INDF,6 ; Test for long addlw 5 ; Yep, it's a long packet IRQINTRecvShort movwf UnilinkCmdLen ; Store the length IRQINTRecvNotCMD1 movf UnilinkTXRX,w ; Get the byte position xorwf UnilinkCmdLen,w ; XOR with the calculated command length andlw 0fh ; and mask - this results in a zero result when finished receiving bnz IRQINTRecvIncomplete ; Packet not ready yet ; Here a packet is actually received a packet, should check the checksum(s) as well, but I don't care right now ; (I need music in my car! :)) ; This is inefficient, I know, I'll improve it later... (Not that it matters, there's plenty of time here ; (there won't be any more communication for at least another 4.8ms)) ; Unilink command parser: ; Check for CMD1 = 01h (System bus commands) movf UnilinkCMD1,w xorlw 01h bnz IRQINTParseNot01 ; Check for 01 00 (Bus Re-Initialization) movf UnilinkCMD2,w ; xorlw 00h bnz IRQINTParseNot0100 clrf UnilinkID ; Clear the existing Unilink ID, if any bcf BUSON_OUT_BIT ; Clear the cascade BUSON pin, not activated again until we have a new ID goto IRQINTParseComplete ; Don't send any reply to this IRQINTParseNot0100 ; Check for 01 02 (Anyone) movf UnilinkCMD2,w xorlw 02h bnz IRQINTParseNot0102 movf UnilinkID,w ; Do I have an ID already? bnz IRQINTParseNot0102 ; Yep, I don't want another one! movlw 10h ; Sending to Master movwf UnilinkRAD movlw 0d0h ; I'm in the MD changer group movwf UnilinkTAD movlw 8ch ; Device discovery command reply movwf UnilinkCMD1 movlw 00h ; 00?? movwf UnilinkCMD2 movlw 6ch ; Hard coded parity (!) movwf UnilinkParity1 movlw 24h ; My internal MD sends 25 here first time, and then 24 when appointed!?? movwf UnilinkData1 movlw 2ch ; 2c?? movwf UnilinkData2 movlw 22h ; 22?? movwf UnilinkData3 movlw 00h ; 00?? movwf UnilinkData4 movlw 0deh ; Hard coded parity 2 (!) movwf UnilinkData5 clrf UnilinkData6 goto IRQINTParseBypassClear ; Don't clear the data, the buffer will be sent as the next packet IRQINTParseNot0102 ; Check for 01 12 (Time poll) movf UnilinkCMD2,w xorlw 12h bnz IRQINTParseNot0112 movf UnilinkRAD,w xorwf UnilinkID,w ; Is it for me? bnz IRQINTParseNot0112 ; Nope clrf UnilinkParity1 movlw 10h ; Sending to Master addwf UnilinkParity1,f movwf UnilinkRAD movf UnilinkID,w ; This is my ID addwf UnilinkParity1,f movwf UnilinkTAD movlw 00h addwf UnilinkParity1,f movwf UnilinkCMD1 movlw 80h ; Idle unless selected btfsc UnilinkSelected,7 clrw addwf UnilinkParity1,f movwf UnilinkCMD2 clrf UnilinkData6 goto IRQINTParseBypassClear ; Don't clear the data, the buffer will be sent as the next packet IRQINTParseNot0112 IRQINTParseNot01 ; Check for CMD1 = 02h (Appoint) movf UnilinkCMD1,w xorlw 02h bnz IRQINTParseNot02 bsf BUSON_OUT_BIT ; Now activate the cascade BUSON pin, to allow others to be discovered movf UnilinkRAD,w ; Get the ID the master has given me movwf UnilinkID ; Store my id movf UnilinkCMD2,w ; Get the bitmask movwf UnilinkBit ; And store it (this is needed when doing slave breaks and actually responding) clrf UnilinkParity1 movlw 10h ; Sending to Master addwf UnilinkParity1,f movwf UnilinkRAD movf UnilinkID,w ; This is my ID addwf UnilinkParity1,f movwf UnilinkTAD movlw 8ch ; Device discovery command again addwf UnilinkParity1,f movwf UnilinkCMD1 movlw 00h addwf UnilinkParity1,f movwf UnilinkCMD2 movf UnilinkParity1,w movwf UnilinkParity2M ; That's the parity when sending medium messages movlw 24h addwf UnilinkParity2M,f movwf UnilinkData1 movlw 2ch ; My internal MD sends 1c here... (external/internal difference) addwf UnilinkParity2M,f movwf UnilinkData2 movlw 22h addwf UnilinkParity2M,f movwf UnilinkData3 movlw 00h addwf UnilinkParity2M,f movwf UnilinkData4 clrf UnilinkData6 goto IRQINTParseBypassClear ; Don't clear the data, the buffer will be sent as the next packet IRQINTParseNot02 ; Check for CMD1 = 87h (Power control) movf UnilinkCMD1,w xorlw 087h bnz IRQINTParseNot87 ; Test for power-on bit (it seems like bit 3 (0x08h) of CMD2 is set when the power is on) btfsc UnilinkCMD2,3 goto IRQINTParse87PowerOn bsf RS232_RI_BIT ; Set this to make RI pin go low (after RS-232 levels) goto IRQINTParseComplete IRQINTParse87PowerOn bcf RS232_RI_BIT ; Clear this to make RI pin go high (waking the computer) goto IRQINTParseComplete IRQINTParseNot87 ; Check for CMD1 = f0h (Source Select) movf UnilinkCMD1,w xorlw 0f0h bnz IRQINTParseNotF0 movf UnilinkCMD2,w xorwf UnilinkID,w ; Check if it's selecting me bnz IRQINTParseF0Deselect bsf UnilinkSelected,7 ; Now we're selected goto IRQINTParseComplete IRQINTParseF0Deselect bcf UnilinkSelected,7 ; Now we're de-selected goto IRQINTParseComplete IRQINTParseNotF0 IRQINTParseComplete ; The CPU ends up here when parsing is complete and it's not interested in sending any reply back to the master ; (that's why we clear out all the packet buffer bytes) ; TODO: Replace this with an FSR access to save space and make the code neater clrf UnilinkRAD clrf UnilinkTAD clrf UnilinkCMD1 clrf UnilinkCMD2 clrf UnilinkParity1 clrf UnilinkData1 clrf UnilinkData2 clrf UnilinkData3 clrf UnilinkData4 clrf UnilinkData5 clrf UnilinkData6 clrf UnilinkData7 clrf UnilinkData8 clrf UnilinkData9 clrf UnilinkParity2 clrf UnilinkZero IRQINTParseBypassClear movlw UnilinkRAD ; Get the pointer to the first byte in the receive buffer movwf UnilinkTXRX ; Store it - this way the next byte that gets received goes into RAD clrf UnilinkCmdLen ; No command length while waiting for a new packet IRQINTRecvIncomplete IRQINTRecvNullByte movf INDF,w movwf DataStore ; Store it so the non-irq code can snoop IRQAfterINT bcf INTCON,INTF ; Clear the IRQ source bit to re-enable INT interrupts again IRQNotINT btfss PIR1,TMR2IF ; Check if it's the TMR2 interrupt (0.5ms timing) goto IRQNotTMR2 ; No it's not, check the other sources ; Slave break opportunity detection here - the logic works as follows: ; Look for a data low period of at least 5 ms (10 loops) ; Look for a data high period of at least 2 ms (4 loops) ; If the Slave Break request bit has been set, issue a slave break by holding the data line low for 5ms (10 loops) ; If a packet would be received the packet handler automatically clears out the SlaveBreakState, which means start all over ; incf Counter,f ; Increment the general purpose counter btfsc SlaveBreakState,5 ; Check if already pulling the data line low goto IRQTMR2SlaveBreak btfsc SlaveBreakState,7 ; Looking for low or high data goto IRQTMR2HighData btfss DATA_BIT ; Looking for a low data line, if it's low, increment state, if it's high, reset state goto IRQTMR2LowDataOK clrf SlaveBreakState ; Got a high data line while waiting for a low one, reset state goto IRQAfterTMR2 ; Leave ISR IRQTMR2HighData btfsc DATA_BIT ; Looking for a high data line, if it's high - increment state, otherwise wait goto IRQTMR2HighDataOK movlw 080h btfss SlaveBreakState,6 ; Test the "first time around" bit clrw ; Not the beginning of the state, have to restart the entire thing now, not just this state andwf SlaveBreakState,f ; Mask out the 1 upper control bits and restart this state goto IRQAfterTMR2 IRQTMR2HighDataOK IRQTMR2LowDataOK bsf SlaveBreakState,6 ; Set the "first time around" bit btfss SlaveBreakState,4 ; Only increment to 0x10 incf SlaveBreakState,f movf SlaveBreakState,w andlw 1fh btfss SlaveBreakState,7 ; Checking whether it's low or high goto IRQTMR2FoundLow xorlw 4 ; It's high now, and if 4 periods have passed we can activate slave break skpz goto IRQAfterTMR2 ; Issue slave break here incf Counter,f ; clrf SlaveBreakState movlw 20h movwf SlaveBreakState bcf DATA_BIT bsf STATUS,RP0 bcf DATA_BIT bcf STATUS,RP0 goto IRQAfterTMR2 IRQTMR2FoundLow xorlw 7 skpz goto IRQAfterTMR2 movlw 80h ; Prepare for state 2, looking for data line high movwf SlaveBreakState goto IRQAfterTMR2 IRQTMR2SlaveBreak movf SlaveBreakState,w andlw 01fh xorlw 4 skpz goto IRQAfterTMR2 bsf STATUS,RP0 bsf DATA_BIT bcf STATUS,RP0 clrf SlaveBreakState IRQAfterTMR2 bcf PIR1,TMR2IF ; Clear the IRQ source bit to re-enable TMR2 interrupts again IRQNotTMR2 ; Finally restore CPU state and return from the ISR ; If I have to save the FSR in the beginning I also need to restore it here... ; movf IRQPCLATH,w ; movwf PCLATH ; Restore PCLATH swapf IRQSTATUS,w movwf STATUS ; Restore STATUS swapf IRQW,f swapf IRQW,w ; Restore W retfie ; Interrupt return subtitl "Main loop" page ;---------------------------------------------------------------- ; Main program begins here. [Called after bootloader, lcdinit and irqinit...] ; org 100h ; Maybe not force this to a specific address later Main movlw high LookUp movwf PCLATH movlw low StartUpText1 ; Show something on the LCD call TxLCD16B MainLoop bcf LCD_RS_BIT ; LCD Command mode movlw 80h ; DisplayRam 0 call TxLCDB bsf LCD_RS_BIT ; movlw '0' movf Counter,w ; Debug timer btfsc PORTA,4 ; Test RST movlw 'R' call TxLCDB ; movlw '0' movf SlaveBreakState,w btfsc PORTB,0 ; Test CLK movlw 'C' call TxLCDB movlw '0' btfsc PORTC,2 ; Test BUSON-IN movlw 'B' call TxLCDB movlw '0' btfsc PORTC,3 ; Test DATA movlw 'D' call TxLCDB movf UnilinkCmdLen,w bz MainDontPrintCmd addlw '0' call TxLCDB MainDontPrintCmd movf DataCount,w ; Load bit counter (if 0 then byte is available) skpz goto MainLoop decf DataCount,f ; Set it non-zero movf DataStore,w call BootTXB ; Send to terminal goto MainLoop ;---------------------------------------------------------------- ; IRQInit - Sets up the IRQ Handler ; Set up Timer2 to generate 2000 interrupts per second, used for timing - 1/16 prescaler and a PR2 reg of 156 (0x9c) is set IRQInit ; Start with clearing the Unilink packet buffer before enabling any interrupts, otherwise the first packet might become corrupt ; TODO: Replace this with FSR access clrf UnilinkSelected clrf UnilinkID clrf UnilinkBit clrf UnilinkCmdLen clrf UnilinkRAD clrf UnilinkTAD clrf UnilinkCMD1 clrf UnilinkCMD2 clrf UnilinkParity1 clrf UnilinkData1 clrf UnilinkData2 clrf UnilinkData3 clrf UnilinkData4 clrf UnilinkData5 clrf UnilinkData6 clrf UnilinkData7 clrf UnilinkData8 clrf UnilinkData9 clrf UnilinkParity2 clrf UnilinkZero clrf DataStore movlw UnilinkRAD ; Get the pointer to the first byte in the receive buffer movwf UnilinkTXRX ; Store it clrf SlaveBreakState ; Zero out the status, we're starting from the beginning ; Fix the output state of RI and BUSON_OUT to a safe default bsf RS232_RI_BIT ; RS232 RI should be inactive (inverted logic, a set bit here gives a negative output) bcf BUSON_OUT_BIT ; BUSON_OUT should be disabled for now, must be appointed first movlw 06h ; Timer2 enabled + 1/16 prescaler movwf T2CON bsf STATUS,RP0 ; Reg bank 1 movlw 09ch ; Timer PR2 reg giving 2000 interrupts per second movwf PR2 bcf RS232_RI_BIT ; Both bits should be outputs bcf BUSON_OUT_BIT ; ; The default behavior of RB0/INT is to interrupt on the rising edge, that's what we use... ; bcf OPTION_REG,INTEDG ; We want RB0 to give us an IRQ on the falling edge bsf INTCON,INTE ; Enable the RB0/INT bsf INTCON,PEIE ; Enable the peripheral interrupts bsf PIE1,TMR2IE ; Enable the Timer2 peripheral interrupt bsf INTCON,GIE ; Enable global interrupts bsf TXSTA,TXEN ; Enable UART TX bcf STATUS,RP0 ; Back to bank 0 bsf RCSTA,SPEN ; Enable serial port bsf RCSTA,CREN ; Enable UART RX return ;---------------------------------------------------------------- ; Initialize LCD Controller... LCDInit clrf PORTB ; First clear PortB data register bsf STATUS,RP0 ; Reg bank 1 movlw 001h ; All but RB0 are outputs. movwf TRISB ; bcf OPTION_REG,NOT_RBPU ; Turn on port B pull-up bcf STATUS,RP0 ; Restore Reg bank 0 ; This is a standard reset sequence for the LCD controller movlw 160 ; Need to delay for at least 15ms, let's go for 16ms delay call DelayW movlw 3 ; Write 3 to the LCD call TxLCD ; Send to LCD movlw 50 ; Need to delay for at least 4.1ms, let's go for 5ms delay call DelayW movlw 3 ; Write 3 to the LCD call TxLCD movlw 10 ; Need to delay for at least 100us, let's go for 1ms delay call DelayW movlw 3 ; Write 3 to the LCD call TxLCD movlw 10 ; Need to delay for at least 40us, let's go for 1ms delay call DelayW movlw 2 ; 4-bit interface requested call TxLCD ; movlw 10 ; Need to delay for at least 40us, let's go for 1ms delay call DelayW ; ; Reset sequence ends here ; From this point no delays are needed, now the BUSY bit is valid and the bus I/F is 4 bits movlw 28h ; Function Select + 4-bit bus + 2-line display call TxLCDB movlw 0ch ; Display Control + LCD On (No cursor) call TxLCDB movlw 01h ; Clear Display call TxLCDB movlw 06h ; Auto Increment cursor position call TxLCDB return ;---------------------------------------------------------------- ; TxLCD16B ; Send a string to the LCD. TxLCD16B movwf Icount bcf LCD_RS_BIT movlw 80h ; DisplayRam 0 call TxLCDB bsf LCD_RS_BIT call TxLCD8B bcf LCD_RS_BIT movlw 80h+40 ; DisplayRam 40 (row 2) call TxLCDB bsf LCD_RS_BIT call TxLCD8B return ;---------------------------------------------------------------- ; TxLCD8B ; Send a string to the LCD. TxLCD8B ; movwf Icount ; Icount = W movlw 8 movwf e_LEN ; Move to e_LEN Txm_lp movf Icount,w ; get the byte call LookUp incf Icount,f ; ...else ++Icount (table index) call TxLCDB ; Send out the byte decfsz e_LEN,f goto Txm_lp return ;---------------------------------------------------------------- ; TxLCDB - send a byte to the LCD TxLCDB movwf TxTemp ; Store byte to send for a while... bcf temp,0 ; Clear my temp bit btfss LCD_RS_BIT ; Check if we try the correct reg goto RxNoProb bcf LCD_RS_BIT bsf temp,0 ; Indicate RS change RxNoProb NotReady call RxLCDB ; Receive byte from LCD, status reg andlw 80h skpz ; If the bit was set, the zero flag is not goto NotReady btfsc temp,0 ; If we had to clear RS reset it now bsf LCD_RS_BIT swapf TxTemp,w ; Hi nibble of data to send in lo w bits call TxLCD ; Send them first... movf TxTemp,w ; Then we have the low nibble in low w bits call TxLCD ; And send that one as well return ;---------------------------------------------------------------- ; RxLCDB - recv a byte from the LCD RxLCDB call RxLCD ; Receive the high nibble movwf LCDWTmp swapf LCDWTmp,f ; Swap it back to file call RxLCD ; Receive the low nibble addwf LCDWTmp,w ; Put the nibbles together and return in W return ;---------------------------------------------------------------- ; TxLCD - send a nibble to the LCD TxLCD movwf LCDWTmp ; Write nibble to tmp bcf LCD_DB4_BIT ; Clear previous data bcf LCD_DB5_BIT ; bcf LCD_DB6_BIT ; bcf LCD_DB7_BIT ; btfsc LCDWTmp,0 ; Test bit 0, transfer a set bit to LCD PORT bsf LCD_DB4_BIT btfsc LCDWTmp,1 ; Test bit 1, transfer a set bit to LCD PORT bsf LCD_DB5_BIT btfsc LCDWTmp,2 ; Test bit 2, transfer a set bit to LCD PORT bsf LCD_DB6_BIT btfsc LCDWTmp,3 ; Test bit 3, transfer a set bit to LCD PORT bsf LCD_DB7_BIT bsf LCD_E_BIT ; And set E to clock the data into the LCD module nop ; Let it settle bcf LCD_E_BIT ; And clear the Enable again. return ; Returns without modifying W ;---------------------------------------------------------------- ; RxLCD - recv a nibble from the LCD RxLCD clrw ; Clear W register, return data in lower 4 bits bsf STATUS,RP0 ; Select 2nd reg bank, now TRIS regs can be accessed bsf LCD_DB4_BIT ; This sets the port bit as an input bsf LCD_DB5_BIT bsf LCD_DB6_BIT bsf LCD_DB7_BIT bcf STATUS,RP0 ; Back at reg bank 0 bsf LCD_RW_BIT ; Set Read mode for the LCD bsf LCD_E_BIT ; And set E to clock the data out of the LCD module nop ; Let the bus settle btfsc LCD_DB4_BIT ; Transfer a set port bit into W addlw 1 btfsc LCD_DB5_BIT ; Transfer a set port bit into W addlw 2 btfsc LCD_DB6_BIT ; Transfer a set port bit into W addlw 4 btfsc LCD_DB7_BIT ; Transfer a set port bit into W addlw 8 bcf LCD_E_BIT ; And clear the Enable again. bcf LCD_RW_BIT ; Set Write mode for the LCD bsf STATUS,RP0 ; Select 2nd reg bank, now TRIS regs can be accessed bcf LCD_DB4_BIT ; Set the port as an output again bcf LCD_DB5_BIT ; bcf LCD_DB6_BIT ; bcf LCD_DB7_BIT ; bcf STATUS,RP0 ; Back at reg bank 0 return ; Returns with data in W ;---------------------------------------------------------------------- ; Delay routines (non-interrupt based, therefore not even close to reliable) ; W=10 gives ~ 1ms of delay ; 1ms=5000 instructions wasted, 100us=500 cycles ; Maximum time waited will be 256*100us=25.6ms DelayW movwf Dcount ; Set delay counter, number of 100us periods to wait DelayOuter movlw 0a5h ; This gives 165 iterations of the inner loop, wastes 495 cycles + these two + one more movwf Dcount2 ; exiting the loop + 3 more for the outer loop = 501 cycles for every Dcount DelayInner decfsz Dcount2,f ; 1 cycle (or two when exiting the loop) goto DelayInner ; 2 cycles decfsz Dcount,f ; Now decrement number of 100us periods and loop again goto DelayOuter return ;---------------------------------------------------------------- ; Data can be stored between 600 and 6ffh... org 600h StartUpText1 DT "----- WJ UniLink" LookUp movwf PCL ; Go to it (this assumes PCLATH == 06h) subtitl "Bootstrap/Bootloader code" page ;---------------------------------------------------------------------- ; Bootstrap code - Allows PIC to flash itself with data from the async port. ; Accepts a standard INHX8 encoded file as input, the only caveat is that the code is slow when writing to memory ; (we have to wait for the flash to complete), and therefore care has to be taken not to overflow the RS232 receiver ; (one good way of solving that is to wait for the echo from the PIC before sending anything else) ; Both program memory and Data EEPROM memory can be programmed, but due to hardware contraints the configuration ; register can't be programmed. That means that any references to the config register in the hex file will be ignored. ; ; Startup @9600bps ; RAM usage for the bootstrap code BootBits equ 7eh ; bit0 1=write 0=read, bit1 1=PGM 0=EE, bit2 0=normal 1=no-op when prog BootAddrL equ 7dh BootAddrH equ 7ch BootDataL equ 7bh BootDataH equ 7ah BootTimerL equ 79h BootTimerM equ 78h BootTimerH equ 77h BootNumBytes equ 76h BootDataVL equ 75h BootDataVH equ 74h BootHEXTemp equ 73h org 738h ; Place the boot code at the top of memory (currently the loader is exactly 200 bytes) Bootstrap bsf STATUS,RP0 ; Access bank 1 bsf TXSTA,TXEN ; Enable UART TX movlw 31 ; Divisor for 9k6 @ 20MHz Fosc movwf SPBRG ; Store bcf STATUS,RP0 ; Back to bank 0 bsf RCSTA,SPEN ; Enable serial port bsf RCSTA,CREN ; Enable UART RX movlw low BootStartText ; Send boot banner to the serial port call BootTXStr movlw 0e8h ; Initialize timeout timer movwf BootTimerL movwf BootTimerM movwf BootTimerH BootTimeout incf BootTimerL,f ; A 24-bit counter skpnz incf BootTimerM,f skpnz incf BootTimerH,f skpnz ; When overflowing here.. goto BootReturn ; ..Exit boot loader, no keypress within timeout period, resume program btfss PIR1,RCIF ; Wait for RX to complete goto BootTimeout call BootRXB xorlw 27 ; ESC skpz goto BootTimeout ; If it wasn't ESC, wait for another key BootFlash movlw low BootFlashText ; OK, flashing it is, send "start" text to serial port call BootTXStr bsf BootBits,1 clrf BootAddrL clrf BootAddrH BootLoop call BootRXB ; First find the ':' xorlw ':' skpz goto BootLoop ; Loop until we find it! call BootRXHEX ; Get one ASCII encoded byte (two chars) movwf BootNumBytes ; This is the number of bytes to be programmed on the line ; Maybe clear cary here? rrf BootNumBytes,f ; Right shift because we're double addressing this 8-bit format ; Note carry should be clear here as there cannot be odd number of bytes in this format call BootRXHEX ; Receive AddrH movwf BootAddrH call BootRXHEX ; Receive AddrL movwf BootAddrL rrf BootAddrH,f ; Fix the addressing again rrf BootAddrL,f bcf BootBits,2 ; Assume we should program bsf BootBits,1 ; And assume we should program flash not ee movf BootAddrH,w xorlw 020h ; Check if it's configuration, which we can't program skpnz ; Skip the bit set if it was false alarm bsf BootBits,2 ; No programming for this line xorlw 001h ; Also check if it's EEPROM memory (first xor 20h then 1 =21h) skpnz ; Skip the bit set instr if not EE data address bcf BootBits,1 ; We should program EE, will ignore the AddrH call BootRXHEX ; Receive Record Type (must be 0 for real records) skpz ; Check if zero goto BootFlashComplete BootLineLoop call BootRXHEX ; Receive low-byte of data word movwf BootDataVL call BootRXHEX ; Receive high-byte of data word movwf BootDataVH btfsc BootBits,2 ; Check whether this line should be programmed at all goto BootWriteSkip bcf BootBits,0 ; Read mode first, verify if we actually have to write call BootEE movf BootDataVL,w xorwf BootDataL,f ; Compare and destroy DataL movwf BootDataL ; Write new data to DataL skpz ; Skip if no difference, have to check high byte as well goto BootWrite ; Jump directly to write movf BootDataVH,w xorwf BootDataH,f ; Compare skpnz ; Skip if no difference, no programming necessary goto BootWriteSkip BootWrite movf BootDataVH,w movwf BootDataH ; Have to put the new H byte data in as well bsf BootBits,0 call BootEE ; Write directly into program mem ; Here a verify can take place, the read-back results are now in DataL/H BootWriteSkip incf BootAddrL,f ; Advance counter to next addr skpnz incf BootAddrH,f ; And add to high byte if needed decfsz BootNumBytes,f goto BootLineLoop goto BootLoop BootFlashComplete BootReturn movlw low BootRunText call BootTXStr bsf STATUS,RP0 ; Reg bank 1 BootReturnWait btfss TXSTA,TRMT ; Wait for last things to flush goto BootReturnWait bcf TXSTA,TXEN ; Disable UART TX bcf STATUS,RP0 ; Back to bank 0 bcf RCSTA,SPEN ; Disable serial port bcf RCSTA,CREN ; Disable UART RX return ; Return to code ;---------------------------------------------------------------------- ; BootTXB - Sends one byte to the UART, waits for transmitter to become ; free before sending BootTXB BootTXW1 btfss PIR1,TXIF ; Wait for TX to empty goto BootTXW1 movwf TXREG ; Send the byte return ;---------------------------------------------------------------------- ; BootTXStr - Sends ASCII string pointed to by W, zero terminated BootTXStr movwf BootAddrL ; Store LSB of text pointer movlw 07h ; MSB of pointer to the text (0700h in this boot loader) movwf BootAddrH movlw 02h ; Select "Read Program Memory" operation movwf BootBits BootTXStrLoop call BootEE ; Lookup char (actually two packed into one word) rlf BootDataL,w ; Shift the MSB out into carry (that's the 2nd char LSB) rlf BootDataH,w ; Shift it into 2nd char call BootTXB ; Send the high byte first movf BootDataL,w ; Get the low byte andlw 07fh ; Mask of the highest bit skpnz ; Stop if zero return call BootTXB ; Send char incf BootAddrL,f ; Increment pointer goto BootTXStrLoop ;---------------------------------------------------------------------- ; BootRXB - Receives one byte from the UART, waits if nothing available BootRXB BootRXW1 btfss PIR1,RCIF ; Wait for RX to complete goto BootRXW1 movf RCREG,w ; Get the recvd byte call BootTXB ; Echo to terminal return ;---------------------------------------------------------------------- ; BootRXHEXNibble - Receives one byte and converts it from ASCII HEX to binary BootRXHEXNibble call BootRXB ; Receive nibble addlw -'A' ; Convert from BCD to binary nibble skpc ; Test if if was 0-9 or A-F, skip if A-F addlw 'A' - 10 - '0' ; It was numeric '0' addlw 10 ; Add 10 (A get to be 0ah etc.) return ;---------------------------------------------------------------------- ; BootRXHEX - Receives two bytes from the UART, waits if nothing available ; Decodes the bytes as ASCII hex and returns a single byte in W BootRXHEX call BootRXHEXNibble movwf BootHEXTemp swapf BootHEXTemp,f ; Swap it up to the high nibble call BootRXHEXNibble addwf BootHEXTemp,w ; And add the two nibbles together return ;---------------------------------------------------------------------- ; BootEE - Reads or writes EE or Flash memory, BootBits specify the ; exact action to take. BootAddrL and BootAddrH has to be initialized ; to the address of choice (0000-003fh for EE and 0000h-07ffh for flash ; The data to be written has to be put in BootDataL and BootDataH, and ; data will be to the same place when read back BootEE bsf STATUS,RP1 ; Select bank 2 (RP0 must be 0) movf BootAddrH,w ; Load desired address movwf EEADRH movf BootAddrL,w movwf EEADR movf BootDataH,w ; And load the data (only used when writing) movwf EEDATH movf BootDataL,w movwf EEDATA bsf STATUS,RP0 ; Go to bank 3 bsf EECON1,EEPGD ; Point to Program Flash mem btfss BootBits,1 ; Test if that was correct or if we have to clear again bcf EECON1,EEPGD ; Point to EE DATA mem btfss BootBits,0 ; Check from read or write goto BootEERD ; Skip the WR if we were going for a read bsf EECON1,WREN ; Enable writes movlw 55h movwf EECON2 movlw 0AAh movwf EECON2 ; Unlock write operation bsf EECON1,WR ; And start a write cycle BootWRLoop btfsc EECON1,WR ; This executes for EE only not flash, waits for WR to finish goto BootWRLoop ; These two instructions gets NOPed when flashing bcf EECON1,WREN ; Finally disable writes again ; Here we read the data back again, can be used as verify BootEERD bsf EECON1,RD ; Start a read cycle nop ; Only necessary for flash read, same thing as when writing above nop ; Except I could use the two words for something useful there.. :) BootEEX bcf STATUS,RP0 ; Back to bank 2 movf EEDATA,w ; Store our EE-data movwf BootDataL movf EEDATH,w movwf BootDataH bcf STATUS,RP1 ; And finally back to bank 0 return ; To produce compact code the end zero byte has to be in the LSB (that means an even number of chars in every string) BootStartText DW 0x2bca,0x216f,0x37f4,0x102d,0x1070,0x3965,0x39f3,0x1045,0x29c3,0x1074,0x37a0,0x336c,0x30f3,0x3400 ; DE "WJBoot - press ESC to flash\x00" BootFlashText DW 0x068a,0x29e5,0x3764,0x1049,0x2748,0x2c38,0x1066,0x34ec,0x32a0,0x376f,0x3bae,0x172e,0x0680 ; DE "\r\nSend INHX8 file now...\r\x00" BootRunText DW 0x068a,0x22f8,0x34f4,0x34ee,0x33a0,0x366f,0x30e4,0x32f2,0x0680 ; DE "\r\nExiting loader\r\x00" ;---------------------------------------------------------------------- ; EE Data (64 bytes), located at 2100h org 2100h ; de 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh END