--- /dev/null
+ title "PIC16F876A Unilink Interface by Werner Johansson (c) 2004-2005"\r
+ subtitl "Definitions"\r
+ list c=132,P=16F876a,R=DEC,F=inhx8m\r
+ include "p16f876a.inc" ; Standard equates & Macros\r
+ ERRORLEVEL 1,-302 ; Get rid of those annoying 302 msgs!\r
+\r
+;----------------------------------------------------------------\r
+; The Configuration Word\r
+ __CONFIG _HS_OSC&_WDT_OFF&_PWRTE_OFF&_BODEN_ON&_LVP_OFF&_CPD_OFF&_WRT_OFF&_DEBUG_OFF&_CP_OFF\r
+\r
+;----------------------------------------------------------------\r
+; HISTORY\r
+;----------------------------------------------------------------\r
+; Version\r
+;\r
+; 0.0 Very first "Fucking No Work!" version\r
+; 0.1 Some receiving works with the new MCU using HW SPI, yay!\r
+;\r
+;----------------------------------------------------------------\r
+\r
+; Unilink BUSON IN (blue) connected to RA4C2/T0CKI\r
+; Unilink DATA (green) connected to RC4(SDI), RC5(SDO) via open collector driver (HW USART)\r
+; Unilink BUSON OUT (blue) connected to RA5 via 100R resistor (this is for daisy-chaining)\r
+; Unilink CLK (yellow) connected to RC3(SCK) (USART CLK)\r
+; Unilink RST (lilac) connected to RB0(INT)\r
+; RS-232 TX from computer connected to RC7/RX\r
+; RS-232 RX to computer connected to RC6/TX\r
+; RS-232 RTS from computer connected to RC2\r
+; RS-232 RI and CTS to computer connected to RC1\r
+; RS-232 INVALID signal from MAX connected to RC0\r
+\r
+; Pin mapping as follows:\r
+\r
+; RA0 Voltage sense (A/D in 0)\r
+; RA1 Amp sense 1 (A/D in 1)\r
+; RA2 Early-Startup sense/Blue LED drive (active low) (RA2 and RA3 have been reversed from the PCB layout!)\r
+; RA3 Amp sense 2 (A/D in 3)\r
+; RA4/T0CKI BUSON IN from Head Unit (can trigger interrupt on clocking?)\r
+; RA5 BUSON OUT to cascade\r
+\r
+; RB0 UNI RST in (interrupt triggered)\r
+; RB1 Enable-PWR output to SEPIC converter\r
+; RB2 Disable-AMP output\r
+; RB3 Enable-AUX output to trigger analog switch relay\r
+; RB4 Sign output from Amp sense 1/Red LED drive, active low\r
+; RB5 Sign output from Amp sense 2/Green LED drive, active low\r
+; RB6 ICSP/ICD reserved\r
+; RB7 ICSP/ICD reserved\r
+\r
+; RC0 INVALID input from MAX3235\r
+; RC1 CTS and RI output\r
+; RC2 RTS input\r
+; RC3 Unilink clock input\r
+; RC4 Unilink data input\r
+; RC5 Unilink data output (drives inverted!)\r
+; RC6 TX output\r
+; RC7 RX input\r
+\r
+;----------------------------------------------------------------\r
+; File register usage\r
+\r
+; Memory from 20h to 7fh (BANK 0 96 bytes)\r
+; a0h to efh (BANK 1 80 bytes)\r
+; 110h to 16fh (BANK 2 96 bytes)\r
+; 190h to 1efh (BANK 3 96 bytes)\r
+; 70-7fh, f0-ffh, 170-17fh and 1f0-1ffh share the same 16 bytes, for ISR!)\r
+\r
+Dcount equ 20h\r
+e_LEN equ 21h\r
+Icount equ 2Dh ; Offset of string to print\r
+TxTemp equ 2Eh ; blahblah\r
+TxTemp2 equ 2Fh ; Blahblah2\r
+\r
+ org 0\r
+ nop ; Leave the first location, just in case\r
+; call Bootstrap ; Call Flash Load routine\r
+; call LCDInit ; Initialize LCD I/F\r
+; call IRQInit ; Set up and start the IRQ handler\r
+ goto Main ; Run the main program loop (skip the IRQ handler)\r
+\r
+ subtitl "IRQ Handler"\r
+;----------------------------------------------------------------\r
+; Interrupt handler always starts at addr 4.\r
+; Let the entire handler stay here instead of branching away\r
+\r
+ org 4 ; Must be on Address 4!\r
+ retfie ; Interrupt return\r
+\r
+\r
+\r
+ subtitl "Main loop"\r
+ page\r
+\r
+ org 100h\r
+Main\r
+ clrf PORTA\r
+ clrf PORTB\r
+ clrf PORTC\r
+ bsf STATUS,RP0 ; Hi Bank\r
+ movlw 04h ; AD mode 4h, 3 ad inputs AN0, 1 and 3, not 2 (!) fix pcb.. :(\r
+ movwf ADCON1\r
+ movlw 0dfh ; RA5 should be outputs...\r
+; movlw 0dbh ; RA2 & RA5 should be outputs...\r
+; movlw 0fbh ; RA2 should be output...\r
+ movwf TRISA ; Yep.\r
+ movlw 0c1h ; RB0, 6 & 7 are inputs.\r
+ movwf TRISB ; Yep\r
+ movlw 9dh ; RC0, 2, 3, 4, 7 are inputs\r
+; movlw 0bdh ; RC0, 2, 3, 4, 7 are inputs\r
+ movwf TRISC\r
+ bcf OPTION_REG,NOT_RBPU ; Turn on port B pull-up\r
+ bcf STATUS,RP0 ; Restore Lo Bank\r
+\r
+ bsf PORTB,1 ; Turn on SEPIC\r
+; bsf PORTA,5 ; test ss shit\r
+\r
+ bsf STATUS,RP0 ; Access bank 1\r
+ bsf TXSTA,TXEN ; Enable UART TX\r
+ movlw 31 ; Divisor for 9k6 @ 20MHz Fosc\r
+ movwf SPBRG ; Store\r
+ bcf STATUS,RP0 ; Back to bank 0\r
+\r
+ bsf RCSTA,SPEN ; Enable serial port\r
+ bsf RCSTA,CREN ; Enable UART RX\r
+\r
+; movlw 'W'\r
+; movwf TXREG ; Test transmission\r
+\r
+ \r
+;WaitRSTHigh\r
+; call UpdateLEDS\r
+; btfss PORTB,0 ; Test RST bit\r
+; goto WaitRSTHigh\r
+\r
+; bsf STATUS,RP0 ; Hi Bank\r
+; bsf TRISA,2 ; RA2 back as input (turn off blue led)\r
+; bcf STATUS,RP0 ; Lo Bank\r
+\r
+RestartCrap\r
+ bcf SSPCON,SSPEN ;disable ssp\r
+\r
+WaitRSTLow\r
+ call UpdateLEDS\r
+;b WaitRSTLow\r
+ btfsc PORTB,0 ; Test RST bit\r
+ goto WaitRSTLow \r
+\r
+WaitBUSONHigh\r
+ call UpdateLEDS\r
+ btfss PORTA,4 ; Test BUSON bit\r
+ goto WaitBUSONHigh \r
+\r
+ bsf STATUS,RP0\r
+; movlw 40h ; Latch on active-to-idle edge (needs ss crap?)\r
+ movlw 00h ; Transfer on idle-to-active edge (and latch on active-to-idle)\r
+ movwf SSPSTAT\r
+ bcf STATUS,RP0\r
+\r
+WaitCLKLow\r
+ call UpdateLEDS\r
+ btfsc PORTC,3 ; SCK input must be low before enabling SSP according to errata sheet (!)\r
+ goto WaitCLKLow\r
+ movlw 25h\r
+; movlw 34h ; fuxx0red ss mode crap\r
+ movwf SSPCON ; Enable SPI slave mode with SCK IDLE low, no _SS control\r
+ clrw\r
+ movwf SSPBUF\r
+\r
+OnceMore\r
+WaitForByte\r
+ call UpdateLEDS\r
+\r
+ btfsc PORTB,0 ; Test RST bit\r
+ goto RestartCrap\r
+\r
+ btfss PORTA,4 ; Test BUSON bit\r
+ goto RestartCrap\r
+\r
+ bsf STATUS,RP0\r
+ btfss SSPSTAT,BF ; Test for buffer complete\r
+ goto WaitForByte\r
+ bcf STATUS,RP0\r
+ movf SSPBUF,w\r
+ xorlw 0ffh ; Invert received data\r
+ movwf TXREG ; Send it out to Async serial\r
+ clrw\r
+ movwf SSPBUF\r
+ goto OnceMore\r
+\r
+meck\r
+ b meck\r
+\r
+UpdateLEDS\r
+; NOTE!!!! This is wrong, never drive the led outputs high as there are other open-collector drivers on these pins!!!\r
+; This is just for debugging, must be removed when hooking things up to the board!!!\r
+ bcf STATUS,RP0\r
+; IO is inverted logic (active low)\r
+; btfsc PORTA,4 ; test buson\r
+ btfss PORTC,4 ; test IO\r
+ bcf PORTB,5 ; turn on green led\r
+; btfss PORTA,4 ; test buson clear\r
+ btfsc PORTC,4 ; test IO\r
+ bsf PORTB,5 ; turn off green led\r
+\r
+; CLK is true logic (active high)\r
+; btfsc PORTB,0 ; Test RST bit\r
+ btfsc PORTC,3 ; test clk\r
+ bcf PORTB,4 ; turn on red led if RST high\r
+; btfss PORTB,0 ; Test RST bit\r
+ btfss PORTC,3 ; test clk\r
+ bsf PORTB,4 ; turn off red led if RST low\r
+\r
+ return\r
+\r
+;----------------------------------------------------------------------\r
+; EE Data (64 bytes), located at 2100h\r
+\r
+ org 2100h\r
+; data 0ffh, 0ffh, 0ffh, 0ffh, 001h, 023h, 045h, 067h\r
+\r
+ END\r
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